TLV320ADC3001_15 Datasheet, PDF (25/86 Pages) Texas Instruments – TLV320ADC3001 Low-Power Stereo ADC With Embedded miniDSP for Wireless Handsets and Portable Audio

www.ti.com
TLV320ADC3001
SLAS548D – OCTOBER 2008 – REVISED SEPTEMBER 2015
A detailed diagram of the audio clock section of the TLV320ADC3001 is shown in Figure 27.
MCLK
BCLK
50 MHz_MAX
13 MHz_MAX
BCLK is an input in slave mode
P0:0x1B(27):3 [ADC Interface Control ] (0h)
P0:0x04(4) [Clock-Gen Muxing ] (0h)
ADC_CLK ADC_MOD_CLK
PLL_CLK_IN REG
PLL_CLKIN
50 MHz_MAX
PLL
x(RxJ.D)/P
P0:0x05(5) [PLL P and R -VAL ] (11h)
P0:0x06(6) [PLL J -VAL ] (4h)
P0:0x07(7) [PLL D -VAL MSB ] (0h)
P0:0x08(8) [PLL D -VAL LSB ] (0h)
P0:0x1D(29)
[ADC Interface Control 2]
(2h)
BDIV_CLKIN
26 MHzMAX
MCLK
BCLK
50 MHz_MAX
13 MHzMAX
PLL_CLK
110 MHz_MAX
P0:0x1E(30)
[BDIV N _VAL ] (1h)
÷N
N = 1, 2, …, 127, 128
P0:0x04(4)[Clock-Gen Muxing ] (0h)
CODEC_CLKIN REG
BCLK
ADC_CLKIN
BCLK is an output in master mode .
P0:0x1B(27):3[ADC Interface Control 1]
÷NADC
P0:0x12(18)
[ADC NADC _VAL ] (1h)
NADC = 1, 2, …, 127, 128
MCLK BCLK
50 MHz_MAX 13 MHz_MAX
PLL_CLK ADC_CLK ADC_MOD_CLK
ADC_CLK
33 MHz_MAX
÷MADC
P0:0x13(19)
[ADC MADC_VAL] (1h)
MADC = 1, 2, …, 127, 128
ADC_MOD_CLK
6.5 MHz_MAX
P0:0x19(25) [CLKOUT MUX ] (0h)
CDIV_CLKIN
110 MHz_MAX
P0:0x1A(26)
÷M
[CLKOUT M_VAL ] (1h)
M = 1, 2, …, 127, 128
÷AOSR
P0:0x14(20)
[ADC AOSR _VAL ] (80h)
AOSR =1, 2, …, 255, 256
CLKOUT (DOUT)
P0:0x35(53)
[DOUT Control ] (1Eh)
ADC_FS
100 kHz_MAX
Note:
MADC x AOSR > IADC
Where IADC number of instructions (Instruction Count) for the ADC MAC engine, it is programmable from 2, 4, …, 510.
Convention:
Page Number: Register Number:{Register Bit}[Register Name](Reset Value)
Figure 27. Audio Clock-Generation Processing
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLV320ADC3001
Submit Documentation Feedback
25