SN74V215 Datasheet, PDF (25/40 Pages) Texas Instruments – 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

WCLK
tENS
WEN
tENH
1
2
tSKEW1
(see Note A)
tSKEW2
(see Note B)
tDS
ÎÎÎÎ _D0–D17
WD
ÎÎÎÎ^tDHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RCLK
tENS
tENS
REN
OE
tOHZ
Q0–Q17
W1
OR
PAE
HF
PAF
IR
tOE
tA
W1 W2
tA
W3
tA
tA
tA
Wm+2
W[m+3]
W[m+4]
W
D – 1+ ₁
2
W
D – 1+ ₂
2
W[D-n-1]
W[D-n]
W[D-n+1] W[D-n+2] W[D-1]
tA
WD
tREF
tPAES
tHF
tPAFS
tWFF
tWFF
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK plus tWFF. If the time between the rising
edge of RLCK and the rising edge of WCLK is less than tSKEW1, the IR assertion might be delayed an extra WCLK cycle.
B. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time may be delayed an extra WCLK cycle.
C. LD is high.
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for SN74V235, and 4097 words
for SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 17. Read Timing With Synchronous Programmable Flags (FWFT Mode)