SN74V215 Datasheet, PDF (16/40 Pages) Texas Instruments – 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
WCLK
ÎÎÎÎ _D0–D17
ÎÎÌÌÌÎÎÌÌÌÎÎÌÌÌÎÎ _WEN
tDS
D0 (First Valid Write)
tENS
tFRL
D1
D2
D3
D4
(see Note A)
tSKEW1
RCLK
tREF
EF
REN ^{ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ tENS}
Q0–Q17
ÎÎÎÎÎÎÎÎÎÎ^tAÎÎÎÎ
tA
D0
D1
tOLZ
tOE
OE
NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the
minimum specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the
empty boundary (EF is low).
B. The first word always is available the cycle after EF goes high.
C. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 4. First-Data-Word Latency with Single Register-Buffered EF (Standard Mode)
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