DSPIC30F5013-20E Datasheet, PDF (25/224 Pages) Texas Instruments – dsPIC30F5011/5013 Data Sheet

3.0 MEMORY ORGANIZATION
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
3.1 Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Program Space
Address Construction, bit 23 allows access to the
Device ID, the User ID and the Configuration bits.
Otherwise, bit 23 is always clear.
dsPIC30F5011/5013
FIGURE 3-1:
PROGRAM SPACE
MEMORY MAP
Reset - GOTO Instruction
Reset - Target Address
000000
000002
000004
Interrupt Vector Table
Vector Tables
Reserved
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Reserved
(Read ‘0’s)
Data EEPROM
(1 Kbyte)
00007E
000080
000084
0000FE
000100
00AFFE
00B000
7FFBFE
7FFC00
7FFFFE
800000
Reserved
© 2006 Microchip Technology Inc.
UNITID (32 instr.)
Reserved
Device Configuration
Registers
8005BE
8005C0
8005FE
800600
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
FEFFFE
FF0000
FFFFFE
DS70116F-page 23