AMC7891_15 Datasheet, PDF (25/41 Pages) Texas Instruments – Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs

AMC7891
www.ti.com
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
When any of the following events occur, the current conversion cycle stops immediately:
• A new trigger is issued.
• The conversion mode changes.
• Either ADC channe register is rewritten.
When a new trigger activates, the ADC starts a new conversion cycle. The trigger should not be issued at the
same time the conversion mode is changed. If a ‘1’ is simultaneously written to the adc_trig bit when changing
the adc_mode bit from ‘0’ to '1', the current conversion stops and immediately returns to the wait for ADC trigger
state.
To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the
conversion process time immediately after the ADC conversion starts.
DOUBLE-BUFFERED ADC DATA REGISTER
The host can access all eight, double-buffered ADCn_data registers, as shown in Figure 28. The conversion
result from the analog input with channel address n, (where n = 0 to 7) is stored in adcn_data[9:0] in straight
binary format. When the conversion of an individual channel is completed, the data is immediately transferred
into the corresponding adcn_tmpry temporary register, the first stage of the data buffer. When the conversion of
the last channel completes, all data in the adcn_tmpry registers is simultaneously transferred to the
corresponding adcn_data[9:0] value, the second stage of the data buffer.
In the case when a data transfer is in progress between any ADCn_data register and the AMC7891 shift register,
all ADCn_data registers are not updated until the data transfer is complete.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Input Range
Selection
adc_trig
(Internal Trigger)
ADC
adc0_tmpry
adc0_data
.
.
.
adc7_tmpry
adc7_data
To Shift
Register
GPIOVDD
adc_ready
10 kW
DAV
Figure 28. ADC Structure
PROGRAMMABLE CONVERSION RATE
The maximum ADC conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 3. The
conversion rate is programmable through adc_rate[1:0] (AMC_config register, [9:8] bits). When more than one
channel is selected, the conversion rate is divided by the number of channels selected in register ADC_enable.
In auto mode, the adc_rate[1:0] value determines the actual conversion rate. In direct mode, adc_rate[1:0] limits
the maximum possible conversion rate. The actual conversion rate in direct mode is determined by the rate of
the conversion trigger. Note that when a trigger is issued, there may be a delay of up to 4 μs to internally
synchronize and initiate the start of the sequential channel conversion process. In both direct- and auto- modes,
when adc_rate[1:0] is set to a value other than the maximum rate ('00'), nap mode is activated between
conversions. By activating nap mode, the AV_DD supply current is reduced.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): AMC7891
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