AMC7891_15 Datasheet, PDF (14/41 Pages) Texas Instruments – Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs

AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
THEORY OF OPERATION
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SERIAL INTERFACE
The AMC7891 is controlled through a flexible four-wire serial interface compatible with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers of the AMC7891
with clock rates up to 30 MHz.
The interface is compatible with most synchronous transfer formats and is configured as a 4 pin interface. SCLK
is the serial interface input clock and CS is serial interface enable. Data is input into SDI and latched into the
24-bit wide SPI shift register on SCLK falling edges, while CS is low. Data is clocked out of SDO on SCLK rising
edges, while CS is low. The contents of the SPI shift register are loaded into the device internal register on a CS
rising edge after some delay. When CS is high, both SCLK and SDI inputs are blocked out and the SDO output
is in high-impedance state.
The serial interface works with both a continuous and a non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock to
latch the data.
Each SPI command is input to SDI and framed by signal CS (Serial Data Enable) asserted low. The frame’s first
byte into SDI is the instruction cycle which identifies the request as a read or write as well as the 7-bit address to
be accessed. The following two bytes in the frame form the data cycle.
CS
SCLK
SDI
Instruction Cycle
Data Cycle
R/W
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Serial Interface Command
Bit 23
Bits[22:16]
R/W. Identifies the communication as a read or write command to the addressed register. Bit =
‘0’ sets the write operation. Bit = ‘1’ sets the read operation.
A[6:0]. Register address; specifies the register to be accessed during the read or write
operation.
Bits[15:0]
D[15:0]. Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address
A[6:0].
If a read command, the data cycle bits are don’t care values.
A read command causes an output on the SDO pin during the next SPI command cycle. The SDO read value
frame is formed by the previous communication instruction cycle and the data read from the specified register.
SPI FRAME
Write Command
Frame
Read Command
Frame
Read Value Frame
Table 1. Serial Data Format
PIN
SDI
SDO
SDI
SDO
SDI
SDO
INSTRUCTION CYCLE
DATA CYLE
Bit 23
Bits [22:16]
Bits [15:0]
0 (R/W)
A[6:0]
Data In[15:0]
Undefined or Read Value Frame depending on previous
command
1 (R/W)
A[6:0]
Don’t care
Undefined or Read Value Frame depending on previous
command
New Write or Read Command Frame
1 (R/W)
A[6:0]
Data Out[15:0]
14
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