TPS65167_07 Datasheet, PDF (24/39 Pages) Texas Instruments – Compact LCD Bias Supply for TFT-LCD TV Panels

TPS65167
TPS65167A
SLVS760B – APRIL 2007 – REVISED OCTOBER 2007
Table 10. Output Capacitor Selection Positive Charge Pump
CAPACITOR
330 nF/35 V
1 µF/35 V
COMPONENT SUPPLIER
Taiyo Yuden GMK212BJ334KG
Taiyo Yuden GMK107BJ105KA
COMMENT
Flying capacitor C9, C20
Output capacitor on POUT
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High Voltage Switch Control (Gate Voltage Shaping)
The output voltage of the TPS65167A remains unchanged with HVS=high. The TPS65167 has a high voltage
switch integrated to provide gate voltage modulation of VGH. If this feature is not required, then the CTRL pin
has to be pulled high or connected to VIN. When the device is disabled or the input voltage is below the
undervoltage lockout (UVLO), then both switches Q4 and Q5 are off, and VGH is discharge by a 1-kΩ resistor
over Q8, as shown in Figure 25.
FB
Power Good
FBP
Power Good
FBN
CTRL
GDLY
EN
Power Good
UVLO
EN
Vref
3.5kW
IDLY
Voltage
clamp
5.8V max
AVIN
Control
CTRL = high Q4 on Q5 off
CTRL = low Q4 off Q5 on
EN = low Q4 and Q5 off,
Q8 on
POUT
Q4
1kW
Q5
Q8
VGH
DRN
Vs
Vs
R13
10kW
R10
1 kW
Option 1
R11
10kW
R12
10kW
Option 2
Option 3
Figure 25. High Voltage Switch (Gate Voltage Shaping) Block TPS65167
To implement gate voltage shaping, the control signal from the LCD timing controller (TCON) is connected to
CTRL. The CTRL pin is activated once the device is enabled, the input voltage is above the under voltage
lockout, all the output voltages (Vs, VGL, VGH) are in regulation and the delay time set by the GDLY pin passed
by. As soon as one of the outputs is pulled below its Power Good level, Q4 and Q5 are turned off, and VGH is
discharged via a 1-kΩ resistor over Q8.
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