TMS320C6727B_07 Datasheet, PDF (24/116 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C – SEPTEMBER 2006 – REVISED OCTOBER 2007
www.ti.com
Table 2-12. Terminal Functions (continued)
SIGNAL NAME
AHCLKR0/AHCLKR1
ACLKR0
AFSR0
AHCLKX0/AHCLKX2
ACLKX0
AFSX0
AMUTE0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/
SPI1_SOMI
AXR0[9]/AXR1[4]/
SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR1
AFSR1
AHCLKX1
ACLKX1
AFSX1
AMUTE1
AHCLKR2
ACLKR2
AFSR2
ACLKX2
AFSX2
AMUTE2/HINT
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
RFP
143
139
141
2
142
144
3
113
115
116
117
119
120
121
122
126
127
130
131
134
135
137
138
9
12
5
7
11
4
-
-
-
-
-
-
111
110
108
107
105
GDH/
ZDH
TYPE ⁽¹⁾
PULL ⁽²⁾
GPIO ⁽³⁾
McASP0, McASP1, McASP2, and SPI1 Serial Ports⁽⁴⁾
DESCRIPTION
B3
IO
-
Y
McASP0 and McASP1 Receive Master Clock
A5
IO
-
Y
McASP0 Receive Bit Clock
B4
IO
-
Y
McASP0 Receive Frame Sync (L/R Clock)
C2
IO
-
Y
McASP0 and McASP2 Transmit Master Clock⁽⁴⁾
A4
IO
-
Y
McASP0 Transmit Bit Clock
A3
IO
-
Y
McASP0 Transmit Frame Sync (L/R Clock)
C1
O
-
Y
McASP0 MUTE Output
A14
IO
-
Y
McASP0 Serial Data 0
B13
IO
-
Y
McASP0 Serial Data 1
A13
IO
-
Y
McASP0 Serial Data 2
B12
IO
-
Y
McASP0 Serial Data 3
A12
IO
-
Y
McASP0 Serial Data 4
B11
IO
-
Y
McASP0 Serial Data 5 or SPI1 Slave Chip Select
A11
IO
-
Y
McASP0 Serial Data 6 or SPI1 Enable (Ready)
B10
IO
-
Y
McASP0 Serial Data 7 or SPI1 Serial Clock
B9
IO
-
Y
McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1
Data Pin Slave Out Master In
A9
IO
-
Y
McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1
Data Pin Slave In Master Out
B8
IO
-
Y
McASP0 Serial Data 10 or McASP1 Serial Data 3
A8
IO
-
Y
McASP0 Serial Data 11 or McASP1 Serial Data 2
B7
IO
-
Y
McASP0 Serial Data 12 or McASP1 Serial Data 1
B6
IO
-
Y
McASP0 Serial Data 13 or McASP1 Serial Data 0
A6
IO
-
Y
McASP0 Serial Data 14 or McASP2 Serial Data 1⁽⁴⁾
B5
IO
-
Y
McASP0 Serial Data 15 or McASP2 Serial Data 0⁽⁴⁾
E1
IO
-
Y
McASP1 Receive Bit Clock
F1
IO
-
Y
McASP1 Receive Frame Sync (L/R Clock)
D1
IO
-
Y
McASP1 Transmit Master Clock
E2
IO
-
Y
McASP1 Transmit Bit Clock
F2
IO
-
Y
McASP1 Transmit Frame Sync (L/R Clock)
D2
O
-
Y
McASP1 MUTE Output
C14
IO
IPD
Y
McASP2 Receive Master Clock
C13
IO
IPD
Y
McASP2 Receive Bit Clock
C12
IO
IPD
Y
McASP2 Receive Frame Sync (L/R Clock)
D11
IO
IPD
Y
McASP2 Transmit Bit Clock
C11
IO
IPD
Y
McASP2 Transmit Frame Sync (L/R Clock)
D10
O
IPD
Y
McASP2 MUTE Output or UHPI Host Interrupt
SPI0, I2C0, and I2C1 Serial Port Pins
B14
IO
-
Y
SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
B15
IO
-
Y
SPI0 Data Pin Slave In Master Out
C16
IO
-
Y
SPI0 Serial Clock or I2C0 Serial Clock
C15
IO
-
Y
SPI0 Slave Chip Select or I2C1 Serial Clock
D16
IO
-
Y
SPI0 Enable (Ready) or I2C1 Serial Data
(4) McASP2 is not available on the C6722B and C6720.
24
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