TL28L92 Datasheet, PDF (24/61 Pages) Texas Instruments – 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

TL28L92
3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter
SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008
Table 3-2. Registers for Channels A and B
REGISTER NAME
Mode
Status
Clock
Command
Receiver FIFO
Transmitter FIFO
CHANNEL A REGISTER
MRnA
SRA
CSRA
CRA
RxFIFOA
TxFIFOA
CHANNEL B REGISTER
MRnB
SRB
CSRB
CRB
RxFIFOB
TxFIFOB
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ACCESS
R/W
R only
W only
W only
R only
W only
Table 3-3. Registers Supporting Both Channels
REGISTER NAME
Input Port Change
Auxiliary Control
Interrupt Status
Interrupt Mask
Counter/Timer Upper Value
Counter/Timer Lower Value
Counter/Timer Preset Upper
Counter/Timer Preset Lower
Input Port
Output Configuration
Set Output Port
Reset Output Port
Interrupt Vector or GP
MNEMONIC
IPCR
ACR
ISR
IMR
CTU
CTL
CTPU
CTPL
IPR
OPCR
SOPR
ROPR
IVR/GP
ACCESS
R
W
R
W
R
R
W
W
R
W
W
W
R/W
3.2 Condensed Register Bit Formats
7
RxWATCHDOG
6
RxINT[2]
Table 3-4. Mode Register 0 (MR0)
5
4
TxINT[1:0]
3
FIFOSIZE
2
BUADRATE
EXTENDED II
1
TEST2
0
BAUDRATE
EXTENDED1
7
RxRTS
control
6
RxINT[1]
Table 3-5. Mode Register 1 (MR1)
5
4
3
2
ERRORMODE
PARITYMODE
PARITYTYPE
1
0
bits per character
Table 3-6. Mode Register 2 (MR2)
7
6
5
4
3
channel mode
RTSN Control Tx CTSN Enable Tx
2
1
0
stop bit length
Table 3-7. Clock Select Register (CSR)
7
6
5
4
receiver clock select code
3
2
1
0
transmitter clock select code
Table 3-8. Command Register (CR)
7
6
5
4
3
2
1
0
channel command code
disable Tx
enable Tx
disable Rx
enable Rx
24
Programming
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