THS6062 Datasheet, PDF (24/31 Pages) Texas Instruments – LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER

THS6062
LOW-NOISE ADSL DUAL DIFFERENTIAL RECEIVER
SLOS228B – JANUARY 1999 – REVISED JUNE 1999
APPLICATION INFORMATION
offset voltage
The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times
the corresponding gains. The following schematic and formula are used to calculate the output offset voltage:
RF
IIB–
RG
+
–
VI
+
VO
RS
ǒ ǒ ǓǓ ǒ ǒ ǓǓ ^IIB+
+ ) " ₎ ) VOO VIO 1
RF
RG
IIB RS 1
RF
RG
" IIB– RF
Figure 45. Output Offset Voltage Model
circuit layout considerations
In order to achieve the high-frequency performance of the THS6062, it is essential that proper printed-circuit
board high frequency design techniques be followed. A general set of guidelines is given below. In addition, a
THS6062 evaluation board is available to use as a guide for layout or for evaluating the device performance.
D Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
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