TCA9555 Datasheet, PDF (24/32 Pages) Texas Instruments – LOW VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

TCA9555
SCPS200A – JULY 2009 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
V_CC
Ramp-Down
V_IN drops below POR levels
V_{CC_TRR_VPOR50}
Ramp-Up
V_{CC_FT}
Time to Re-Ramp
V_{CC_RT}
Figure 19. V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC
Time
Table 1 specifies the performance of the power-on reset feature for TCA9555 for both types of power-on reset.
Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES⁽¹⁾
V_{CC_FT}
V_{CC_RT}
V_{CC_TRR_GND}
V_{CC_TRR_POR50}
V_{CC_GH}
V_{CC_GW}
V_PORF
V_PORR
PARAMETER
Fall rate
Rise rate
Time to re-ramp (when V_CC drops to GND)
Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV)
Level that V_CCP can glitch down to, but not cause a functional
disruption when V_{CCX_GW} = 1 µs
Glitch width that will not cause a functional disruption when
V_{CCX_GH} = 0.5 × V_CCx
Voltage trip point of POR on falling V_CC
Voltage trip point of POR on rising V_CC
See Figure 18
See Figure 18
See Figure 18
See Figure 19
See Figure 20
See Figure 20
MIN TYP
0.1
0.1
1
1
0.7
(1) T_A = –40°C to 85°C (unless otherwise noted)
MAX
2000
2000
1.2
10
1.4
UNIT
ms
ms
µs
µs
V
µs
V
V
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 20 and Table 1 provide more
information on how to measure these specifications.
V_CC
V_{CC_GH}
V_{CC_GW}
Figure 20. Glitch Width and Glitch Height
Time
V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the
registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based
on the V_CC being lowered to or from 0. Figure 21 and Table 1 provide more details on this specification.
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