MSC1202Y3RHHTG4 Datasheet, PDF (24/92 Pages) Texas Instruments –
Precision Analog-to-Digital Converter and Current-Output Digital-to-Analog Converter

MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
ADC ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK,
SFR F6h) and gain (PGA). The relationship is:
Impedance
(W)
+
1
f_SAMP @
C_S
ǒ Ǔ ǒ Ǔ A_IN Impedance (W) +
1MHz
ACLK Frequency
@
7MW
PGA
where
ACLK
frequency
(f _ACLK)
+
f_CLK
ACLK )
1
and
f _MOD
+
f_ACLK
64
.
NOTE: The input impedance for PGA = 128 is the same as
that for PGA = 64 (that is, 7MΩ/64).
Figure 9 shows the basic input structure of the MSC120x.
R_SWITCH
(3kΩ typical)
A_IN
C_S
Sampling Frequency = f_SAMP
PGA
1, 2, 4
8
16
32
64, 128
f_SAMP
f_MOD
2 × f_MOD
4 × f_MOD
8 × f_MOD
16 × f_MOD
AGND
f_MOD =
f_ACLK
64
High Impedance
> 1GΩ
PGA
1
2
4 to 128
C_S
9pF
18pF
36pF
Figure 9. Analog Input Structure (without Buffer)
ADC PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective
resolution of the ADC. For instance, with a PGA of 1 on a
±2.5V full-scale range (FSR), the ADC can resolve to
1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can
resolve to 75nV. With a PGA of 1 on a ±2.5V FSR, it would
require a 26-bit ADC to resolve 75nV, as shown in Table 1.
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Table 1. ENOB versus PGA (Bipolar Mode)
PGA
SETTING
FULL-
SCALE
RANGE
(V)
MSC1200
MSC1201
ENOB(1)
AT 10HZ
(BITS)
MSC1202
ENOB(1)
UP TO
200HZ
(BITS)
RMS
INPUT-REFERRED
NOISE
MSC1200
MSC1201
(nV)
MSC1202
(mV)
1
±2.5
21.7
16
1468
76.3
2
±1.25
21.5
15.6
843
38.1
4
±0.625
21.4
15.5
452
19.1
8
±0.313
21.2
15.4
259
9.5
16
±0.156
20.8
15.4
171
4.8
32
±0.078
20.4
15.3
113
2.4
64
±0.039
20
15.2
74.5
12
128
±0.019
19
14.2
74.5
0.6
(1) _{ENOB = Log2(FSR/RMS Noise) = Log2(2}24_{) − Log2(σCODES)}
= 24 − Log₂(σ_CODES)
ADC OFFSET DAC
The analog output from the PGA can be offset by up to half
the full-scale range of the ADC by using the ODAC register
(SFR E6h). The ODAC (Offset DAC) register is an 8-bit
value; the MSB is the sign and the seven LSBs provide the
magnitude of the offset.
ADC MODULATOR
The modulator is a single-loop, 2nd-order system. The
modulator runs at a clock speed (f_MOD) that is derived from
CLK using the value in the Analog Clock register (ACLK,
SFR F6h). The data output rate is:
Data
Rate
+
f _DATA
+
f _MOD
Decimation
Ratio
where
f _MOD
+
f_CLK
(ACLK ) 1)
@
64
+
f_ACLK
64
.
and Decimation Ratio is set in [ADCON3:ADCON2]
ADC CALIBRATION
The offset and gain errors in the MSC120x, or the complete
system, can be reduced with calibration. Calibration is
controlled through the ADCON1 register (SFR DDh), bits
CAL2:CAL0. Each calibration process takes seven t_DATA
periods (data conversion time) to complete. Therefore, it
takes 14 t_DATA periods to complete both an offset and gain
calibration.
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