BQ24153A Datasheet, PDF (24/43 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger

bq24153A
bq24156A, bq24158
SLUSAB0 – OCTOBER 2010
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Safety Timer in Boost Mode
At the beginning of boost operation, the IC starts a 32-second timer that is reset by the host using the I²C
interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is
automatically set to “0” after the 32-second timer is reset. Once the 32-second timer expires, the IC turns off the
boost converter, enunciates the fault pulse from the STAT pin and sets fault status bits in the status register. The
fault condition is cleared by POR or host control.
Protection in Boost Mode
Output Overvoltage Protection
The IC provides a built-in over-voltage protection to protect the device and other components against damage if
the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM
converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once
VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active
status.
Output Overload Protection
The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is
over loaded. Once the over load condition is detected, Q1 operates in linear mode to limit the output current. If
the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is
detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out
fault pulse in STAT pin. The boost will not start until the host clears the fault register.
Battery Overvoltage Protection
During boosting, when the battery voltage is above the battery over voltage threshold, V_BATMAX, or below the
minimum battery voltage threshold, V_BATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets
fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above V_BATMIN, the boost
will start after the host sets OPA_MODE to “1” or OTG pin stays in active status.
STAT Pin Boost Mode
During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault
conditions, a 128-ms pulse is sent out to notify the host.
High Impedance Mode
When control bit of HZ-MODE is set to “1” and OTG pin is not in active status, the IC operates in high impedance
mode, with the input impedance of the VBUS pin being higher than 217kΩ. In high impedance mode, a low
power 32-second timer is enabled when the battery voltage is below V_(LOWV) to monitor if the host control is
available or not. If the low power 32 second timer expires, the IC operates in 15 minute mode and the low power
32 second timer is disabled. In 15 minute mode, when VBUS is below UVLO, the IC operates in high impedance
mode regardless of the HZ_MODE bit's setting.
SERIAL INTERFACE DESCRIPTION
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I²C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
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