AM3715CBP Datasheet, PDF (236/280 Pages) Texas Instruments – Sitara ARM Microprocessors

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
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Table 6-95. HSUSB1 and HSUSB2 Timing Requirements—12-bit Master Mode^{(1) (2)} (continued)
NO.
PARAMETER
HSU6 t_h(clkH-dV)
Hold time, input data hsusbx_data[7:0] valid after output clock
hsusbx_clk rising edge
(1) In hsusbx, x is equal to 1 or 2.
(2) See Section 4.3.4, Processor Clocks.
OPP100
MIN
MAX
–0.52
UNIT
ns
Table 6-96. HSUSB1 and HSUSB2 Switching Characteristics—12-bit Master Mode^{(1) (3)}
NO.
PARAMETER
HSU0
HSU1
f_p(clk)
t_J(clk)
t_d(clkH-stpV)
Frequency, output clock hsusbx_clk
Jitter standard deviation⁽²⁾, output clock hsusbx_clk
Delay time, output clock hsusbx_clk rising edge to output stop signal
hsusbx_stp valid
t_{d(clkH-stpIV)}
Delay time, output clock hsusbx_clk rising edge to output stop signal
hsusbx_stp invalid
HSU2 t_d(clkH-dV)
Delay time, output clock hsusbx_clk rising edge to output data
hsusbx_data[7:0] valid
t_d(clkH-dIV)
Delay time, output clock hsusbx_clk rising edge to output data
hsusbx_data[7:0] invalid
t_R(d)
Rise time, output data hsusbx_data[7:0]
t_F(d)
Fall time, output data hsusbx_data[7:0]
(1) In hsusbx, x is equal to 1 or 2.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) See Section 4.3.4, Processor Clocks.
OPP100
MIN
MAX
60
400
12.81
1.95
12.81
1.95
0
0
UNIT
MHz
ps
ns
ns
ns
ns
ns
ns
HSU0
hsusbx_clk
hsusbx_stp
hsusbx_dir
and
hsusbx_nxt
hsusbx_data[7:0]
HSU1
HSU1
HSU2
Data_OUT
HSU2
HSU3
HSU5
Data_IN
HSU4
HSU6
(1) In hsusbx, x is equal to 1 or 2.
Figure 6-52. HSUSB1 and HSUSB2—12-bit Master Mode
6.6.5 Inter-Integrated Circuit Interface (I²C)
SWPS038-081
NOTE
For more information, see Multimaster High-Speed I2C Controller chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4).
The multi-master I²C peripheral provides an interface between two or more devices via an I²C serial bus.
236 Timing Requirements and Switching Characteristics
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