AM3715CBP Datasheet, PDF (227/280 Pages) Texas Instruments – Sitara ARM Microprocessors

AM3715, AM3703
www.ti.com
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
(1) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.
(2) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
– mcspix_clk⁽¹⁾ phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– mcspix_clk⁽¹⁾ phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device
Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.
(3) P = mcspix_clk clock period
(4) Case P = 20.8 ns, A = (TCS+0.5)*P⁽³⁾ (TCS is a bit field of MSPI_CHCONFx[26:25] register).
Case P > 20.8 ns, A = TCS*P⁽³⁾ (TCS is a bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of
the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
(5) B = TCS*P⁽³⁾ (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4).
(6) See Section 4.3.4, Processor Clocks.
Table 6-80. McSPI3 Timing Requirements—Master Mode⁽¹⁾
NO.
PARAMETER
SM2
t_{su(SOMIV-CLKAE)} Setup time, mcspi3_somi valid before mcspi3_clk
active edge
SM3
t_{h(SOMIV-CLKAE)} Hold time, mcspi3_somi valid after mcspi3_clk active
edge
(1) See Section 4.3.4, Processor Clocks.
OPP100
MIN
MAX
1.5
2.8
OPP50
MIN
MAX
4.3
5.9
UNIT
ns
ns
Table 6-81. McSPI3 Switching Characteristics—Master Mode^{(1) (2) (6)}
NO.
SM0
SM1
1/t_c(CLK)
t_w(CLKH)
t_R(clk)
t_F(clk)
SM4 t_d(CLK-SIMO)
SM5 t_d(CSn-CLK)
SM6 t_d(CLK-CSn)
SM7 t_d(csn-simo)
PARAMETER
Frequency, mcspi3_clk
Pulse duration, mcspi3_clk high or low
Rise time, output clock mcspi3_clk
CBP
Balls:
AE2 /
AE13
CBP
Ball: H26
Fall time, output clock mcspi3_clk
CBP
Balls:
AE2 /
AE13
CBP
Ball: H26
Delay time, mcspi3_clk active edge to mcspi3_simo
shifted
Delay time, mcspi3_csi active to
mcspi3_clk first edge
Modes 1
and 3
Modes 0
and 2
Delay time, mcspi3_clk last edge to
mcspi3_csi inactive
Modes 1
and 3
Modes 0
and 2
Delay time, mcspi3_csi active edge to
mcspi3_simo shifted
Modes 0
and 2
OPP100
MIN
MAX
24
0.45*P⁽³⁾ 0.55*P⁽³⁾
7.33
4.31
6.77
4.0
–2.1
A⁽⁴⁾ – 4.4
B⁽⁵⁾ – 4.4
B⁽⁵⁾ – 4.4
A⁽⁴⁾ – 4.4
11.3
11.3
OPP50
MIN
MAX
12
0.45*P⁽³⁾ 0.55*P⁽³⁾
7.31
4.30
6.71
–5.3
A⁽⁴⁾ –
10.1
B⁽⁵⁾ –
10.1
B⁽⁵⁾ –
10.1
A⁽⁴⁾ –
10.1
4.0
23.6
23.6
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 227
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