TMS370C686AFNT Datasheet, PDF (22/45 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx8x
8-BIT MICROCONTROLLER
SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997
programmable timer 1 (continued)
Figure 7 shows the Timer 1 dual-compare mode block diagram. The annotations on the diagram identify the
register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in
the T1CTL2 register.
T1 SW
RESET
T1CTL2.0
Prescaler
Clock
Source
T1CC.15-0
16-Bit _LSB
Capt/Comp
Register ^MSB
T1CNTR.15-0
Compare=
LSB _16-Bit
Counter
16
MSB
Reset
T1C1
RST ENA
T1CTL4.4
Compare=
T1C.15-0
16-Bit LSB
Compare
Register MSB
T1C2 INT FLAG
T1CTL3.6
T1CTL3.1
T1C2 INT ENA
T1C1 INT FLAG
T1CTL3.5
T1CTL3.0
T1C1 INT ENA
Output
Enable
T1CTL4.5
T1C2 OUT ENA
T1CTL4.6
T1C1 OUT ENA
T1CTL4.3
T1CR OUT ENA
T1PC2.7-4
T1PWM
T1PC2.3-0
T1IC/CR
T1CTL4.1
T1CR
RST ENA
Edge
Select
T1CTL4.0
T1EDGE DET ENA
T1CTL4.2
T1EDGE POLARITY
T1 OVRFL INT FLAG
T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1EDGE INT FLAG
T1CTL3.7
T1CTL3.2
T1EDGE INT ENA
T1 PRIORITY
T1PRI.6
0 _{Level 1 Int}
1 _{Level 2 Int}
Figure 7. Dual-Compare Mode
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