TMS370C686AFNT Datasheet, PDF (13/45 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx8x
8-BIT MICROCONTROLLER
SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997
interrupts (continued)
One of the system interrupts is generated by on-chip peripheral functions, and three external interrupts are
supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input
polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as
either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked
by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation. It,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the
interrupt function is not required (INT1 can be similarly configured as an input pin).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{INTERRUPT SOURCE}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{External RESET}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Watchdog Overflow}
Oscillator Fault Detect
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{External INT1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{External INT2}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{External INT3}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Timer 1 Overflow}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 1 Compare 1
Timer 1 Compare 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Timer 1 External Edge}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Timer 1 Input Capture 1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Watchdog Overflow}
Table 8. Hardware System Interrupts
INTERRUPT FLAG
COLD START
WD OVRFL INT FLAG
OSC FLT FLAG
INT1 FLAG
INT2 FLAG
INT3 FLAG
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC1 INT FLAG
WD OVRFL INT FLAG
SYSTEM
INTERRUPT
RESET‡
INT1‡
INT2‡
INT3‡
T1INT§
VECTOR
ADDRESS
7FFEh, 7FFFh
7FFCh, 7FFDh
7FFAh, 7FFBh
7FF8h, 7FF9h
PRIORITY†
1
2
3
4
7FF4h, 7FF5h
5
† _{Relative priority within an interrupt level}
‡ _{Release microcontroller from STANDBY and HALT low-power modes}
§ _{Release microcontroller from STANDBY low-power mode}
privileged operation and EEPROM write-protection override
The TMS370Cx8x family is designed with significant flexibility to enable the designer to software-configure the
system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of
operation ensures the integrity of the system configuration once it is defined for an application. Following a
hardware reset, the TMS370Cx8x operates in the privileged mode, where all peripheral file registers have
unrestricted read / write access, and the application program configures the system during the initialization
sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is
set to 1 to enter the nonprivileged mode, thus disabling write operations to specific configuration-control bits
within the PF. Table 9 displays the system-configuration bits, which are write-protected during the nonprivileged
mode and must be configured by software prior to exiting the privileged mode.
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