DRV8846_15 Datasheet, PDF(22/35 Page) Texas Instruments – DRV8846 Dual H-Bridge Stepper Motor Driver

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

DRV8846_15 Datasheet, PDF (22/35 Pages) Texas Instruments – DRV8846 Dual H-Bridge Stepper Motor Driver

◁

DRV8846

SLLSEK2 â JUNE 2014

www.ti.com

8.3.6.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled and the nFAULT pin is driven

low. After the die temperature falls to a safe level, operation automatically resumes. The nFAULT pin is released

after operation has resumed.

8.3.6.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the

device is disabled, and all internal logic is reset. Operation resumes when VM rises above the UVLO rising

threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has

resumed.

Fault

VM UVLO

OCP

TSD

Error Report

nFAULT unlatched

Table 9. Fault Behavior

H-Bridge

Disabled

Internal Circuits

Shut down

Operating

Recovery

System and fault clears on recovery

System and fault clears on recovery and motor is driven

after time, tRETRY

System and fault clears on recovery

8.4 Device Functional Modes

The DRV8846 device is active unless the nSLEEP pin is driven low. In sleep mode, the VINT regulator is

disabled and the H-bridge FETs are disabled (Hi-Z). The time tSLEEP must elapse after a falling edge on the

nSLEEP pin before the device enters sleep mode. The DRV8846 is brought out of sleep mode by bringing the

nSLEEP pin high. The time tWAKE must elapse, after nSLEEP is brought high, before the outputs change state.

If the nENBL pin is brought high, the H-bridge outputs are disabled, but the internal logic is still active. An

appropriate edge on STEP (depending on the step mode) advances the indexer, but the outputs do not change

state until nENBL is driven low.

When VM falls below the VM UVLO threshold, VUVLO, the output driver, internal logic, and VINT regulator are

reset.

Mode

Operating

Disabled

Sleep

Fault

Table 10. Operating Modes

Condition

4 V < VM < 18 V

nSLEEP pin = 1

nENBL = 0

4 V < VM < 18 V

nSLEEP pin = 1

nENBL = 1

4 V < VM < 18 V

nSLEEP pin = 0

Any fault condition met

H-Bridge

Operating

Disabled

VINT

Operating

Disabled

Depends on fault

Indexer

Operating

Disabled

Depends on fault

Submit Documentation Feedback

Product Folder Links: DRV8846

▷