TPS40200-HT_15 Datasheet, PDF (21/48 Pages) Texas Instruments – WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

TPS40200-HT
www.ti.com
Component Selection
SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012
Table 4. Design Parameters
SYMBOL
V_IN
V_OUT
V_OUT
V_RIPPLE
V_OVER
V_UNDER
I_OUT
I_SCP
PARAMETER
Input voltage
Output voltage
Line regulation
Load regulation
Output voltage
Line regulation
Load regulation
Output ripple voltage
Output overshoot
Output undershoot
Output current
Short-circuit current trip point
Efficiency
F_S
Switching frequency
TEST CONDITION
I_OUT at 2.5 A
±0.2% V_OUT
±0.2% V_OUT
I_OUT at 2.5 A
±0.2% V_OUT
±0.2% V_OUT
At maximum output current
For 2.5-A load transient from 2.5 A to 0.25 A
For 2.5-A load transient from 0.25 A to 2.5 A
At nominal input voltage and maximum output
current
MIN
8
3.200
3.293
3.293
4.85
4.990
4.990
0.125
3.75
NOM
12
3.3
3.3
3.3
5
5
5
60
100
60
90
300
MAX
16
3.400 ⁽¹⁾
3.307
3.307
5.150 ⁽¹⁾
5.010
5.010
2.5
5.00
UNIT
V
V
V
V
V
V
V
mV
mV
mV
A
A
%
kHz
(1) Set-point accuracy is dependent on external resistor tolerance and the IC reference voltage. Line and load regulation values are
referenced to the nominal design output voltage.
FET Selection Criteria
• The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that
can equal the input voltage. Since the R_DSON of the FET rises with breakdown voltage, select a FET with as
low a breakdown voltage as possible. In this case, a 30-V FET was selected.
• The selection of a power FET’s size requires knowing both the switching losses and dc losses in the
application. AC losses are all frequency dependent and directly related to device capacitances and device
size. Conversely, dc losses are inversely related to device size. The result is an optimum where the two types
of losses are equal. Since device size is proportional to R_DSON, a starting point is to select a device with an
R_DSON that results in a small loss of power relative to package thermal capability and overall efficiency
objectives.
• In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss
budget of 0.916 W. Total FET losses must be small, relative to this number.
The dc conduction loss in the FET is given by:
P_DC
=
I_r
2
ms
´
R_DSON
(8)
The rms current is given by:
1
I_rms
=
é
ê_{D ´}
ê
ë
ççæ^{IOUT 2}
è
+
DI_pp ²
12
÷öúù
÷øúû
2
(9)
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