TPS40200-HT_15 Datasheet, PDF (17/48 Pages) Texas Instruments – WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

TPS40200-HT
www.ti.com
SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012
MOSFET Gate Drive
The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When
the driver pulls the gate charge of the FET, it is controlling to –8 V, the drive current folds back to a low level so
that high power dissipation only occurs during the turnon period of the FET. This feature is particularly valuable
when turning on a FET at high input voltages, where leaving the gate drive current on would otherwise cause
unacceptable power dissipation.
Undervoltage Lockout (UVLO) Protection
UVLO protection ensures proper startup of the device only when the input voltage has exceeded minimum
operating voltage. Undervoltage protection incorporates hysteresis, which eliminates hiccup starting in cases
where input supply impedance is high.
VDD
8
TPS40200
545k
200K
-
+
+ 1.3V
RUN
36K
GND
5
Figure 30. Undervoltage Lockout
Undervoltage protection ensures proper startup of the device only when the input voltage has exceeded
minimum operating voltage. The UVLO level is measured at the VDD pin with respect to GND. Startup voltage is
typically 4.3 V, with approximately 200 mV of hysteresis. The part shuts off at a nominal 4.1 V. As shown in
Figure 30, when the input VDD voltage rises to 4.3 V , the 1.3-V comparator’s threshold voltage is exceeded and
a RUN signal occurs. Feedback from the output closes the switch and shunts the 200-kΩ resistor so that an
approximate 200-mV lower voltage, or 4.1 V, is required before the part shuts down.
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