TLV320AIC21 Datasheet, PDF (21/62 Pages) Texas Instruments – Low Power,Low Voltage 1.1V to 3.6V I/O Highly-Integrated Programmable 16-Bit 26-KSPS Dual Channel Codec

Where:
FS is the frame-sync frequency.
#Device is the number of the codec channels in cascade. (#Device = 2 for stand-alone AIC21)
Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
3.6.2 Serial Data Out (DOUT)
DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data word
is the ADC conversion result. In the control frame, the data is the register read results when requested by the
read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all zeroes. Valid
data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The first bit transmitted
on the falling edge of FS is the MSB of valid data.
3.6.3 Serial Data In (DIN)
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of first SCLK
after FS. In a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used,
the LSB (D0) of every DAC channel is set to 1 to switch from the continuous data transfer mode to the programming
mode. In a control frame, the data is the control and configuration data that sets the device for a particular function
as described in Section 3.9, Control Register Programming.
3.6.4 Frame-Sync FS
The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin is
connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).
Data is valid on the falling edge of the FS signal.
The frequency of FS is defined as the sampling rate of the TLV320AIC21 and derived from the master clock MCLK
as followed (see Section 3.1 Operating Frequencies for details):
FS = MCLK / (16× P × N × M)
SCLK
(Output)
0
1
29
30
31
32 SCLKs
FS
DIN/DOUT
(16 Bit)
D15
D14
D1
D0
D15
D14
MSB
LSB MSB
D1 D0
LSB
Master (CH 1)
Slave (CH 2)
Figure 3–1. Timing Diagram for FS in the Continuous Transfer Mode
3.6.5 Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP receives all frame-sync pulses from the master though the master’s FS. The master’s FSD
is output to the first slave and the first slave’s FSD is output to the second slave device and so on. Figure 3–2 shows
the cascade of four TLV320AIC21s in which the closest one to DSP is the master and the rest are slaves. The FSD
output of each device is input to the FS terminal of the succeeding device. Figure 3–3 shows the FSD timing sequence
in the cascade.
3–5