TLV320AIC21 Datasheet, PDF (15/62 Pages) Texas Instruments – Low Power,Low Voltage 1.1V to 3.6V I/O Highly-Integrated Programmable 16-Bit 26-KSPS Dual Channel Codec

2.3 Definitions and Terminology
Data Transfer
Interval
Signal Data
Frame Sync
Frame Sync and
Sampling Period
f_s
ADC Channel
DAC channel
Dxx
DSxx
d
PGA
IIR
FIR
The time during which data is transferred from DOUT and to DIN. The interval is 16 shift
clocks, and the data transfer is initiated by the falling edge of the FS signal.
This refers to the input signal and all of the converted representations through the ADC
channel and the signal through the DAC channel to the analog output. This is contrasted with
the purely digital software control data.
Frame sync refers only to the falling edge of the signal FS that initiates the data transfer
interval
Frame sync and sampling period is the time between falling edges of successive FS signals.
The sampling frequency
ADC channel refers to all signal processing circuits between the analog input and the digital
conversion result at DOUT.
DAC channel refers to all signal processing circuits between the digital data word applied to
DIN and the differential output analog signal available at OUTP and OUTM.
Bit position in the primary data word (xx is the bit number)
Bit position in the secondary data word (xx is the bit number)
The alpha character d represents valid programmed or default data in the control register
format (see Section 3.2, Secondary Serial Communication) when discussing other data bit
portions of the register.
Programmable gain amplifier
Infinite impulse response
Finite impulse response
2–3