OPA2822UG4 Datasheet, PDF (21/33 Pages) Texas Instruments – Dual, Wideband, Low-Noise Operational Amplifier

As the Typical Characteristics show, until the fundamental
signal reaches very high frequencies or power levels, the
limit to SFDR will be 2nd-harmonic distortion rather than the
negligible 3rd-harmonic component. Focusing then on the
second harmonic, increasing the load impedance improves
distortion directly. However, operating differentially offers
the most significant improvement in even-order distortion
terms. For example, the Electrical Characteristics show that
a single channel of the OPA2822, delivering 2V_PP at 1MHz
into a 200Ω load, will typically show a 2nd-harmonic product
at –92dBc versus the 3rd-harmonic at –102dBc. Changing
the configuration to a differential driver where each output
still drives 2V_PP results in a 4V_PP total differential output into
a 400Ω differential load, giving the same single-ended load
of 200Ω for each amplifier. This configuration drops the
2nd-harmonic to –103dBc and the 3rd-harmonic to approxi-
mately –105dBc—an overall dynamic range improvement
of more than 10dB.
For general distortion analysis, remember that the total
loading on the amplifier includes the feedback network; in the
noninverting configuration, this is the sum of R_F + R_G, while
in the inverting configuration this additional loading is simply
R_F. Increasing the output voltage swing increases the har-
monic distortion directly. A 6dB increase in the output swing
will generally increase the 2nd-harmonic 12dB and the 3rd-
harmonic 18dB. Increasing the signal gain will also generally
increase both the 2nd- and 3rd-harmonics because the loop
gain decreases at higher gains. Again, a 6dB increase in
voltage gain will increase the 2nd-harmonic distortion by
approximately 6dB. The distortion characteristic curves for
the OPA2822 show little change in the 3rd-harmonic distor-
tion versus gain. Finally, the overall distortion generally
increases as the fundamental frequency increases due to the
rolloff in the loop gain with frequency. Conversely, the distor-
tion will improve going to lower frequencies, down to the
dominant open-loop pole at approximately 50kHz. This will
give essentially unmeasurable levels of harmonic distortion
in the audio band.
The OPA2822 exhibits an extremely low 3rd-order harmonic
distortion. This also gives exceptionally good 2-tone 3rd-
order intermodulation intercept as shown in the Typical
Characteristics. This intercept curve is defined at the 50Ω
load when driven through a 50Ω matching resistor to allow
direct comparisons to RF MMIC devices. This network at-
tenuates the voltage swing from the output pin to the load by
6dB. If the OPA2822 drives directly into the input of a high-
impedance device, such as an ADC, this 6dB attenuation
does not occur. Under these conditions, the intercept will
improve by at least 6dBm. The intercept is used to predict the
intermodulation spurs for two closely spaced frequencies. If
the two test frequencies, f₁ and f₂, are specified in terms of
average and delta frequency, f_O = (f₁ + f₂)/2 and ∆_F = |f₂ – f₁|,
the two, 3rd-order, close-in spurious tones will appear at
f_O ± 3 • ∆_F. The difference between two equal test-tone power
levels and the spurious intermodulation power levels is given
by ∆dBc = 2 • (IM3 – P_O), where IM3 is the intercept taken
from the Typical Specification and P_O is the power level in
dBm at the 50Ω load for either one of the two closely spaced
test frequencies. For example, at 1MHz in a gain of +2
configuration, the OPA2822 exhibits an intercept of 57dBm
at a matched 50Ω load. If the full envelope of the two
frequencies needs to be 2V_PP, each tone will be set to 4dBm.
The 3rd-order intermodulation spurious tones will then be
2 • (57 – 4) = 106dBc below the test-tone power level
(–102dBm). If this same 2V_PP 2-tone envelope were deliv-
ered directly into the input of an ADC without the matching
loss or loading of the 50Ω network, the intercept would
increase to at least 63dBm. With the same signal and gain
conditions but now driving directly into a light load, the
spurious tones would then be at least 2 • (63 – 4) = 118dBc
below the test-tone power levels.
DC ACCURACY AND OFFSET CONTROL
The OPA2822 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection, high
power-supply rejection, and low input offset voltage and bias
current offset errors. To take full advantage of the low input
offset voltage (±1.2mV maximum at 25°C), careful attention
to input bias current cancellation is also required. The high-
speed input stage for the OPA2822 has relatively high input
bias current (8µA typical into the pins) but with a very close
match between the two input currents, typically 100nA input
offset current. The total output offset voltage may be reduced
considerably by matching the source impedances looking out
of the two inputs. For example, one way to add bias current
cancellation to the circuit of Figure 1 would be to insert a
175Ω series resistor into the noninverting input from the 50Ω
terminating resistor. If the 50Ω source resistor is DC coupled,
this will increase the source impedance for the noninverting
input bias current to 200Ω. Since this is now equal to the
impedance looking out of the inverting input (R_F || R_G), the
circuit will cancel the bias current effects, leaving only the
offset current times the feedback resistor as a residual DC
error term at the output. Using a 402Ω feedback resistor, the
output DC error due to the input bias currents will now be less
than 0.7µA • 402Ω = 0.28mV over the full temperature range.
This is significantly lower than the contribution due to the
input offset voltage. At a gain of +2, the maximum input offset
voltage is 1.5mV, giving a total maximum output offset of
(±3mV ± 0.28mV) = ±3.3mV over the –40°C to +85°C
temperature range (for the circuit of Figure 1, including the
additional 175Ω resistor at the noninverting input).
THERMAL ANALYSIS
The OPA2822 will not require heatsinking or airflow under
most operating conditions. Maximum desired junction tem-
perature will limit the maximum allowed internal power dissi-
pation as described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by T_A + P_Dθ_JA.
The total internal power dissipation (P_D) is the sum of the
quiescent power (P_DO) and additional power dissipated in the
output stage (P_DL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P_DL will depend on the required
OPA2822
21
SBOS188E
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