TMS320C6746 Datasheet, PDF (209/216 Pages) Texas Instruments – Fixed/Floating-Point DSP

www.ti.com
Category
Analysis
TMS320C6746 Fixed/Floating-Point DSP
SPRS591 – JUNE 2009
Table 6-119. DSP Debug Features (continued)
Hardware Feature
Watch point
Watch point with Data
Counters/timers
External Event Trigger In
External Event Trigger Out
Availability
Up to 4 watch points, which are shared with HWBPs, and can also be used as 2 watch
points with data (32 bits)
Up to 2, Which can also be used as 4 watch points.
1x64-bits (cycle only) + 2x32-bits (water mark counters)
1
1
6.28.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
PIN
TRST
TCK
TMS
TDI
TDO
EMU0
EMU1
TYPE
I
I
I
I
O
I/O
I/O
Table 6-120. JTAG Port Description
NAME
Test Logic Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
Emulation 1
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to be reset
along with the IEEE 1149.1 interface
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
Scan data output of the device
Channel 0 trigger + HSRTDX
Channel 1 trigger + HSRTDX
6.28.2 Scan Chain Configuration Parameters
Table 6-121 shows the TAP configuration details required to configure the router/emulator for this device.
Router Port ID
17
19
Default TAP
No
No
Table 6-121. JTAG Port Description
TAP Name
C674x
ETB
Tap IR Length
38
4
The router is revision C and has a 6-bit IR length.
6.28.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
Submit Documentation Feedback
Peripheral Information and Electrical Specifications 209