TMS320C6746 Datasheet, PDF (177/216 Pages) Texas Instruments – Fixed/Floating-Point DSP

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TMS320C6746 Fixed/Floating-Point DSP
SPRS591 – JUNE 2009
6.21 Host-Port Interface (UHPI)
6.21.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16).
6.21.2 HPI Peripheral Register Description(s)
Table 6-95. HPI Control Registers
BYTE ADDRESS
0x01E1 0000
0x01E1 0004
0x01E1 0008
0x01E1 000C
0x01E1 0010
0x01E1 0014
0x01E1 0018
0x01E1 001C
0x01E1 0020
0x01E1 0024
01E1 0028
01E1 002C
01E1 0030
01E1 0034
01E1 0038
01E1 000C - 01E1 07FF
ACRONYM
PID
PWREMU_MGMT
-
GPIO_EN
GPIO_DIR1
GPIO_DAT1
GPIO_DIR2
GPIO_DAT2
GPIO_DIR3
GPIO_DAT3
-
-
HPIC
HPIA
(HPIAW) ⁽¹⁾
HPIA
(HPIAR) ⁽¹⁾
-
REGISTER DESCRIPTION
Peripheral Identification Register
HPI power and emulation management register
Reserved
General Purpose IO Enable Register
General Purpose IO Direction Register 1
General Purpose IO Data Register 1
General Purpose IO Direction Register 2
General Purpose IO Data Register 2
General Purpose IO Direction Register 3
General Purpose IO Data Register 3
Reserved
Reserved
HPI control register
HPI address register
(Write)
HPI address register
(Read)
Reserved
COMMENTS
The CPU has read/write access
to the PWREMU_MGMT register.
The Host and the CPU both have
read/write access to the HPIC
register.
The Host has read/write access
to the HPIA registers. The CPU
has only read access to the HPIA
registers.
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
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Peripheral Information and Electrical Specifications 177