TMS320C6745CPTPA3 Datasheet, PDF (207/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
www.ti.com
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
Table 5-110. DSP Debug Features
Category
Hardware Feature
Availability
Software breakpoint
Unlimited
Basic Debug
Hardware breakpoint
Up to 10 HWBPs, including:
4 precise⁽¹⁾ HWBPs inside DSP core and one of them is
associated with a counter.
2 imprecise⁽¹⁾ HWBPs from AET.
4 imprecise⁽¹⁾ HWBPs from AET which are shared for
watch point.
Watch point
Up to 4 watch points, which are shared with HWBPs,
and can also be used as 2 watch points with data (32
bits)
Analysis
Watch point with Data
Counters/timers
Up to 2, Which can also be used as 4 watch points.
1x64-bits (cycle only) + 2x32-bits (watermark counters)
External Event Trigger In
1
External Event Trigger Out
1
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
5.31.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
PIN
TRST
TCK
TMS
TDI
TDO
EMU[0]
TYPE
I
I
I
I
O
I/O
Table 5-111. JTAG Port Description
NAME
Test Logic Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device
to be reset along with the IEEE 1149.1 interface
This is the test clock used to drive an IEEE 1149.1 TAP state machine
and logic.
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
Scan data output of the device
Channel 0 trigger + HSRTDX
5.31.2 Scan Chain Configuration Parameters
Table 5-112 shows the TAP configuration details required to configure the router/emulator for this device.
Router Port ID
17
Default TAP
No
Table 5-112. JTAG Port Description
TAP Name
C674x
Tap IR Length
38
The router is ICEpick revision C and has a 6-bit IR length.
Copyright © 2008–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 207
Submit Documentation Feedback
Product Folder Links: TMS320C6745 TMS320C6747