TMS320C6745CPTPA3 Datasheet, PDF (127/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
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SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
Table 5-50. McASP1 Switching Characteristics⁽¹⁾
NO.
9
t_c(AHCLKRX)
10 t_w(AHCLKRX)
11 t_c(ACLKRX)
12 t_w(ACLKRX)
13 t_{d(ACLKRX-AFSRX)}
14 t_{d(ACLKX-AXRV)}
15 t_{dis(ACLKX-AXRHZ)}
PARAMETER
Cycle time, AHCLKR1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
Pulse duration, AHCLKR1 internal, AHCLKR1 output
Pulse duration, AHCLKR1 external, AHCLKR1 output
Pulse duration, AHCLKX1 internal, AHCLKX1 output
Pulse duration, AHCLKX1 external, AHCLKX1 output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output⁽⁷⁾
Delay time, ACLKX1 internal, AFSX output
Delay time, ACLKR1 external input, AFSR output⁽⁷⁾
Delay time, ACLKX1 external input, AFSX output
Delay time, ACLKR1 external output, AFSR output⁽⁷⁾
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
Delay time, ACLKX1 external output, AXR1[n] output
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n] output
Disable time, ACLKX1 external output, AXR1[n] output
MIN
25
25
25
25
(AHR/2) – 2.5⁽²⁾
(AHR/2) – 2.5⁽²⁾
(AHX/2) – 2.5⁽³⁾
(AHX/2) – 2.5⁽³⁾
greater of 2P or 25⁽⁴⁾
greater of 2P or 25⁽⁴⁾
greater of 2P or 25⁽⁴⁾
greater of 2P or 25⁽⁴⁾
(AR/2) – 2.5⁽⁵⁾
(AR/2) – 2.5⁽⁵⁾
(AX/2) – 2.5⁽⁶⁾
(AX/2) – 2.5⁽⁶⁾
0.5
0.5
3.4
3.4
3.4
3.4
0.5
3.4
3.4
0.5
3.9
3.9
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
MAX UNIT
ns
ns
ns
ns
6.7
6.7
13.8
ns
13.8
13.8
13.8
6.7
13.8 ns
13.8
6.7
13.8 ns
13.8
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Peripheral Information and Electrical Specifications 127
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