OMAP3515_08 Datasheet, PDF (207/262 Pages) Texas Instruments – Applications Processor

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OMAP3515/03 Applications Processor
SPRS505B – FEBRUARY 2008 – REVISED JULY 2008
Table 6-57. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive
Mode ⁽¹⁾
NO.
PARAMETER
B2
t_d(CLKAE-FSV)
Delay time, mcbsp1_clkr / mcbspx_clkx active edge to
mcbsp1_fsr / mcbspx_fsx valid
1.15 V
MIN
MAX
0.7
14.8
1.0 V
MIN
MAX
0.7
29.6
UNIT
ns
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-58. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode⁽¹⁾
NO.
B3
t_{su(DRV-CLKXAE)}
B4
t_{h(CLKXAE-DRV)}
B5
t_{su(FSXV-CLKXAE)}
B6
t_{h(CLKXAE-FSXV)}
PARAMETER
Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
Hold time, mcbspx_dr valid after
mcbspx_clkx active edge
Master
Slave
Setup time mcbspx_fsx valid before mcbspx_clkx active
edge
Hold time mcbspx_fsx valid after mcbspx_clkx active
edge
1.15 V
MIN
MAX
2.7
3.7
1
0.4
3.7
0.5
1.0 V
MIN
MAX
7.7
7.9
1
0.4
7.9
0.5
UNIT
ns
ns
ns
ns
ns
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60
Table 6-59. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2 t_{d(CLKXAE-FSXV)} Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
0.7
16.6
0.7
33.1
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60
Table 6-60. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode⁽¹⁾
NO.
PARAMETER
B3 t_{su(DRV-CLKXAE)} Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
B4
t_{h(CLKXAE-DRV)}
Hold time, mcbspx_dr valid after mcbspx_clkx Master
active edge
Slave
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before mcbspx_clkx active
edge
B6 t_{h(CLKXAE-FSXV)} Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
1.15 V
MIN
MAX
5.6
5.8
1
0.4
5.8
0.5
1.0 V
MIN
MAX
12
12.2
1
0.4
12.2
0.5
UNIT
ns
ns
ns
ns
ns
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 207