OMAP3515_08 Datasheet, PDF (139/262 Pages) Texas Instruments – Applications Processor

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OMAP3515/03 Applications Processor
SPRS505B – FEBRUARY 2008 – REVISED JULY 2008
4.2 Output Clock Specifications
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:
• sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be
controlled by software or externally using sys_clkreq control. When the device is in the off state, the
sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the
device. The off state polarity of sys_clkout1 is programmable.
• sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,
332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off
state polarity is programmable. This output is active only when the core domain is active.
Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.
Table 4-10. sys_clkout1 Output Clock Electrical Characteristics
NAME
f
C_I
DESCRIPTION
Frequency
Load capacitance⁽¹⁾
f(max) = 38.4 MHz
f(max) = 26 MHz
MIN
TYP
12, 13, 16.8, 19.2, 26, or 38.4
37
50
(1) The load capacitance is adapted to a frequency.
MAX
UNIT
MHz
pF
Table 4-11 details the sys_clkout1 output clock timing characteristics.
Table 4-11. sys_clkout1 Output Clock Switching Characteristics
NAME
f
CO1
1 / CO0
t_w(CLKOUT1)
DESCRIPTION
Frequency
Pulse duration, sys_clkout1 low or high
CO2
CO3
t_R(CLKOUT1)
t_F(CLKOUT1)
Rise time, sys_clkout1⁽¹⁾
Fall time, sys_clkout1⁽¹⁾
(1) With a load capacitance of 25 pF.
MIN
TYP
MAX
12, 13, 16.8, 19.2, 26, or 38.4
0.40 *
t_c(CLKOUT1)
0.60 *
t_c(CLKOUT1)
5.5
5.5
UNIT
MHz
ns
ns
ns
sys_clkout
CO0
CO1
Figure 4-7. sys_clkout1 System Output Clock
CO1
030-014
Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.
Table 4-12. sys_clkout2 Output Clock Electrical Characteristics
NAME
DESCRIPTION
f
Frequency, sys_clkout2
C_L
Load capacitance⁽¹⁾
f(max) = 166 MHz
(1) The load capacitance is adapted to a frequency.
MIN
TYP
2
8
MAX
322
12
UNIT
MHz
pF
Table 4-13 details the sys_clkout2 output clock timing characteristics.
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CLOCK SPECIFICATIONS 139