TMS320DM6446 Datasheet, PDF (203/214 Pages) Texas Instruments – Digital Media System on-Chip

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TMS320DM6446
Digital Media System on-Chip
SPRS283 – DECEMBER 2005
Table 5-93. Timer 2 (Watchdog) Registers (continued)
HEX ADDRESS RANGE
0x01C2 1C04
0x01C2 1C10
0x01C2 1C14
0x01C2 1C18
0x01C2 1C1C
0x01C2 1C20
0x01C2 1C24
0x01C2 1C28
0x01C2 1C2C - 0x01C2 1FFF
ACRONYM
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
WDTCR
-
DESCRIPTION
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
Timer 2 Period Register 34
Timer 2 Control Register
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
5.21.2 Timer Electrical Data/Timing
Table 5-94. Timing Requirements for Timer Input⁽¹⁾⁽²⁾ (see Figure 5-66)
NO.
1
t_c(TIN)
Cycle time, TIM_IN
2
t_w(TINPH)
Pulse duration, TIM_IN high
3
t_w(TINPL)
Pulse duration, TIM_IN low
4
t_t(TIN)
Transition time, TIM_IN
(1) P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
(2) C = TIM_IN cycle time in ns. For example, when TIM_IN frequency is 27 MHz, use C = 37.037 ns
1
2
3
4
4
TIM_IN
Figure 5-66. Timer Timing
-594
MIN MAX
4P
0.45C 0.55C
0.45C 0.55C
0.05C
UNIT
ns
ns
ns
ns
5.22 Pulse Width Modulator (PWM)
The 3 DM6446 Pulse Width Modulator (PWM) peripherals support the following features:
• Period counter
• First-phase duration counter
• Repeat count for one-shot operation
• Configurable to operate in either one-shot or continuous mode
• Buffered period and first-phase duration registers
• One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or
high-to-low).
• One-shot operation generates N+1 periods of waveform, N being the repeat count register value
• Emulation support
The register memory maps for PWM0/1/2 are shown in Table 5-95, Table 5-96, and Table 5-97.
Peripheral and Electrical Specifications 203