TMS320C6474FGUN Datasheet, PDF (203/214 Pages) Texas Instruments – TMS320C6474 Multicore Digital Signal Processor

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TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BF 3110
02BF 3114
02BF 3118
02BF 311C
02BF 3120
02BF 3124
02BF 3128
02BF 312C
02BF 3130
02BF 3134
02BF 3138
02BF 313C
02BF 3140
02BF 3144
02BF 3148
02BF 314C
02BF 3150
02BF 3154
02BF 3158
02BF 315C
02BF 3160
02BF 3164 - 02BF 31FC
02BF 3200
02BF 3204
02BF 3208
02BF 320C
02BF 3210 - 02BF BFFC
02BF C000
02BF C004
ACRONYM
EE_EV2_LINK_IMS_B
EE_COMMON_IMS_EV2
EE_EV3_LINK_IMS_A
EE_EV3_LINK_IMS_B
EE_COMMON_IMS_EV3
EE_COMMON_MSK_SET_EV0
EE_COMMON_MSK_SET_EV1
EE_EV2_LINK_MSK_SET_A
EE_EV2_LINK_MSK_SET_B
EE_COMMON_MSK_SET_EV2
EE_EV3_LINK_MSK_SET_A
EE_EV3_LINK_MSK_SET_B
EE_COMMON_MSK_SET_EV3
EE_COMMON_MSK_CLR_EV0
EE_COMMON_MSK_CLR_EV1
EE_EV2_LINK_MSK_CLR_A
EE_EV2_LINK_MSK_CLR_B
EE_COMMON_MSK_CLR_EV2
EE_EV3_LINK_MSK_CLR_A
EE_EV3_LINK_MSK_CLR_B
EE_COMMON_MSK_CLR_EV3
-
EE_INT_VECT_EV0
EE_INT_VECT_EV1
EE_INT_VECT_EV2
EE_INT_VECT_EV3
-
VD_RD_BUSERR
VD_WR_BUSERR
REGISTER NAME
Event Enable Event 2 Interrupt Source Masked Status
Register B
Event Enable Common Interrupt Event 2 Masked Status
Register
Event Enable Event 3 Interrupt Source Masked Status
Register A
Event Enable Event 3 Interrupt Source Masked Status
Register B
Event Enable Common Interrupt Event 3 Masked Status
Register
Event Enable 0 Common Interrupt Mask Set Register
Event Enable 1 Common Interrupt Mask Set Register
Event 2 Link Interrupt Source Mask Set Register A
Event 2 Link Interrupt Source Mask Set Register B
Event Enable 2 Common Interrupt Mask Set Register
Event 3 Link Interrupt Source Mask Set Register A
Event 3 Link Interrupt Source Mask Set Register B
Event Enable 3 Common Interrupt Mask Set Register
Event Enable 0 Common Interrupt Mask Clear Register
Event Enable 1 Common Interrupt Mask Clear Register
Event 2 Link Interrupt Mask Clear Register A
Event 2 Link Interrupt Mask Clear Register B
Event Enable 2 Common Interrupt Mask Clear Register
Event 3 Link Interrupt Mask Clear Register A
Event 3 Link Interrupt Mask Clear Register B
Event Enable 3 Common Interrupt Mask Clear Register
Reserved
Event Enable Interrupt Vector Register for AI_EVENT0
Event Enable Interrupt Vector Register for AI_EVENT1
Event Enable Interrupt Vector Register for AI_EVENT2
Event Enable Interrupt Vector Register for AI_EVENT3
Reserved
VBUSP DMA Read Bus Interface Status Registers
VBUSP DMA Write Bus Interface Status Registers
7.22.2 Antenna Electrical Data/Timing
The TMS320C6474 Hardware Design Guide application report (literature number SPRAAW7) specifies a
complete AIF interface solution for the C6474 device as well as a list of compatible AIF devices. TI has
performed the simulation and system characterization to ensure all AIF interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
TI only supports designs that follow the board design guidelines outlined in the SPRAAW7
application report.
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Peripheral Information and Electrical Specifications 203
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