XIO1100 Datasheet, PDF (20/36 Pages) Texas Instruments – X1 PCI Express
Serial Link

Electrical Characteristics
PARAMETER
ZTX–DC
Transmitter dc imped-
ance
TERMINALS
TXP, TXN
MIN NOM
40
MAX
UNIT
Ω
COMMENTS
Required TXP as well as TXN dc impedance during all
states
CTX
TXP, TXN
75
AC coupling capacitor
200 nF All transmitters are ac–coupled and are required on the
PWB.
NOTES: 4. No test load is necessarily associated with this value.
5. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX
UIs.
6. A TTX–EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX–JITTER–MAX = 0.25 UI for the
transmitter collected over any 250 consecutive TX UIs. The TTX–EYE–MEDIAN–to–MAX–JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected
over any 250 consecutive TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the
point in time where the number of jitter points on either side is approximately equal, as opposed to the averaged time value.
7. The transmitter input impedance results in a differential return loss greater than or equal to 12 dB and a common mode return
loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to
all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the P and N lines. Note
that the use of the series capacitors CTX is optional for the return loss measurement.
8. Measured between 20% and 80% at transmitter package terminals into a test load for both VTXP and VTXN
3.4 PCI Express Differential Receiver Input Ranges
PARAMETER
UI
Unit interval
TERMINALS MIN
RXP, RXN 399.88
NOM MAX
400 400.12
UNIT
ps
COMMENTS
Each UI is 400 ps ±300 ppm. UI does not account
for SSC−dictated variations.
See Note 9.
VRX–DIFFp–p
Differential input peak–to–peak
voltage
RXP, RXN
0.175
1.200 V VRX–DIFFp–p = 2*|VRXP − VRXN|
See Note 10.
TRX–EYE
RXP, RXN
0.4
Minimum receiver eye width
UI The maximum interconnect media and transmitter
jitter that can be tolerated by the receiver is derived
as
TRX–MAX–JITTER = 1 − TRX–EYE = 0.6 UI.
See Notes 10 and 11.
NOTES: 9. No test load is necessarily associated with this value.
10. Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when
taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from
3500 consecutive UI is used as a reference for the eye diagram.
11. A TRX–EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect
collected any 250 consecutive UIs. The TRX–EYE–MEDIAN–to–MAX–JITTER specification ensures a jitter distribution in which the
median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive
TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the
number of jitter points on either side is approximately equal, as opposed to the averaged time value. If the clocks to the RX and
TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UIs must be used as the reference
for the eye diagram.
12. The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV
and the N line biased to −300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency
range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for
return loss measurements is 50 Ω to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50–Ω
probes). The use of the series capacitors CTX is optional for the return loss measurement.
13. Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect
state (the initial state of the LTSSM), there is a 5–ms transition time before receiver termination values must be met on the
unconfigured lane of a port.
14. The RX dc common mode impedance that exists when no power is present or PCI Express reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at
300 mV above the RX ground.
June 2006
SLLS690B
15