XIO1100 Datasheet, PDF (14/36 Pages) Texas Instruments – X1 PCI Express
Serial Link

Description
Table 2−5. XIO1100 Terminals (Continued)
TERMINAL
TX_ELECIDLE
N9
I/O
DESCRIPTION
I
Forces TXN/TXP outputs to electrical idle.
When de−asserting low while in P0 state (POWERDOWN[1:0] = 00), indicates that
valid data is on the TXDATA bus and that this data should be transmitted.
When asserted high while in P0s state (POWERDOWN[1:0] = 01), always asserted
for P0s state.
When asserted high while in P1 state (POWERDOWN[1:0] = 10), always asserted
for P1 state.
TX_COMPLIANCE
N8
I
Transmit Compliance Pattern
When asserted high, the XIO1100 sets the running disparity to negativity. Used
when transmitting the compliance pattern.
TX_DET_LOOPBACK L5
I
Begin Receive Detect/Begin Loop−Back
Input to device to either begin a receive detect operation or enter loop−back mode.
RX_CLK
B8
O Synchronous Output Clock for RX_DATA[15:0] and RX_DATAK[1:0] outputs
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, RX_CLK is a SDR clock, and RX_DATA[15:0] and RX_DATAK[1:0] are
latched on the rising edge of RX_CLK.
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, RX_CLK is a DDR clock and RX_DATA[7:0] and RX_DATAK[0] are latched
on both the rising and falling edge of the RX_CLK. RX_DATA[15:8] and
RX_DATAK[1] are not used.
RX_CLK is also used as the internal PCLK for the XIO1100.
RX_DATA[15:0]
A7, B6, A6, B5,
A5, B4, A4, A3,
C1, C2, D2, D1,
E2, E1, F2, F1
O Parallel Data Receive Bus
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, RX_DATA[15:0] is latched on the rising edge of the RX_CLK. RX_DATA[7:0]
represents the first symbol received, and RX_DATA[15:8] represents the second
symbol received from the RXN and RXP differential signal pair.
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, RX_DATA[7:0] is latched on both the rising edge and falling edge of the
RX_CLK. The data on RX_DATA[7:0] during the rising edge of the RX_CLK
represents the first symbol received, and the data on RX_DATA[7:0] during the
falling edge of the RX_CLK represents the second symbol received from the RXN
and RXP differential signal pair.
RX_DATA[15:8] is not used.
RX_DATAK[1:0]
B7, A8
O Data/Control for the parallel data receive bus
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, the state of RX_DATAK[0] corresponds to RX_DATA[7:0], and RX_DATAK[1]
corresponds to RX_DATA[15:8].
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, the state of RX_DATA[0] corresponds to the data on RX_DATA[7:0] during the
same phase of the clock. RX_DATAK[1] is not used.
A value of zero indicates that the corresponding RXDATA bits contain data
information. A value of one indicates that the corresponding RXDATA bits contain a
control byte.
NOTE: The TI−PIPE interface can operate at either 1.5 V or 1.8 V, depending on the voltage level of VDD_IO. If VDD_IO is 1.5 V, the TI−PIPE
interface operates at 1.5 V level. If VDD_IO is 1.8 V, the TI−PIPE interface operates at 1.8 V level.
June 2006
SLLS690B
9