TMS370CX5X Datasheet, PDF (20/77 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
privileged operation and EEPROM write-protection override (continued)
Table 13. Privileged Bits
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _REGISTER†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _NAME
LOCATION
CONTROL BIT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SCCRO
P010.5
P010.6
PF AUTOWAIT
OSC POWER
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SCCR1
P011.2
P011.4
MEMORY DISABLE
AUTOWAIT DISABLE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SCCR2
P012.0
P012.1
P012.3
P012.4
P012.6
P012.7
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SPIPRI
P03F.5
P03F.6
P03F.7
SPI ESPEN
SPI PRIORITY
SPI STEST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _SCIPRI
P05F.4
P05F.5
P05F.6
P05F.7
SCI ESPEN
SCIRX PRIORITY
SCITX PRIORITY
SCI STEST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _T1PRI
P04F.6
P04F.7
T1 PRIORITY
T1 STEST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _T2APRI
P06F.6
P06F.7
T2A PRIORITY
T2A STEST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _P07F.5
AD ESPEN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _ADPRI
P07F.6
AD PRIORITY
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ P07F.7
AD STEST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{† The privileged bits are shown in a bold typeface in Table 15.}
The write-protect override (WPO) mode provides an external hardware method for overriding the
write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V
input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the
programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data
EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.
The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT / STANDBY bit in SCCR2 controls which low-power mode is entered.
In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial
communications interface remain active. System processing is suspended until a qualified interrupt (hardware
RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial
communications interface 1) is detected.
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