TLC2274-HT Datasheet, PDF (20/29 Pages) Texas Instruments – TLC2274-HT Advanced LinCMOS Rail-to-Rail Operational Amplifier

TLC2274-HT
SGLS416 – JANUARY 2015
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
As per Equation 1:
Table 2. Design Parameters
Improvement in Phase Margin
0
7.15
17.43
32.12
UGBW (kHz)
1000
1000
1000
1000
R null (Ω)
0
20
50
100
CL (pF)
1000
1000
1000
1000
8.2.2 Detailed Design Procedure
A smaller series resistor (R_null) at the output of the device (see Figure 47) improves the gain and phase margins
when driving large capacitive loads. Figure 48 and Figure 49 show the effects of adding series resistances of 10
Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds a
zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, Equation 1 can be used.
Δφ_m1 = tan^–1 (2 × π × UGBW × R_null × C_L)
where
• Δφm1 = Improvement in phase margin
• UGBW = Unity-gain bandwidth frequency
• Rnull = Output series resistance
• CL = Load capacitance
(1)
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 47). To use
equation 1, UGBW must be approximated from Figure 47. Using Equation 1 alone overestimates the
improvement in phase margin, as illustrated in Figure 51. The overestimation is caused by the decrease in the
frequency of the pole associated with the load, thus providing additional phase shift and reducing the overall
improvement in phase margin. Using Figure 47, with Equation 1 enables the designer to choose the appropriate
output series resistance to optimize the design of circuits driving large capacitance loads.
8.2.3 Application Curves
T_A = 25°C
75°
V_DD = ± 5 V
T_A = 25°C
60°
45°
R_null = 100 Ω
R_null = 50 Ω
R_null = 20 Ω
30°
10 kΩ
15°
10 kΩ
VI
0°
10
VDD +
Rnull
VDD −
R_null = 0
CL _{Rnull = 10 Ω}
100
1000
C_L − Load Capacitance − pF
10000
15
12
9
6
3
0
10
V_DD = 5 V
A_V = 1
R_L = 10 kΩ
T_A = 25°C
100
1000
C_L − Load Capacitance − pF
10000
Figure 48. Phase Margin vs Load Capacitance
Figure 49. Gain Margin vs Load Capacitance
20
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