THS770006_10 Datasheet, PDF (20/36 Pages) Texas Instruments – Broadband, Fully-Differential, 14-/16-Bit ADC DRIVER AMPLIFIER

THS770006
SBOS520 – JULY 2010
www.ti.com
Driving Capcitive Loads
The THS770006 is tested as described previously, with the data shown in the typical graphs. As a result of the
fixed gain architecture of the device, the only practical means to avoid stability problems such as
overshoot/ringing, gain peaking, and oscillation when driving capacitive loads is to place small resistors in series
with the outputs (R_O) to isolate the phase shift caused by the capacitive load from the feedback loop of the
amplifier. The Typical Characteristics graphs show recommended values for an optimally flat frequency response
with maximum bandwidth. Smaller values of R_O can be used if more peaking is allowed, and larger values can
be used to - reduce the bandwidth.
Driving ADCs
The THS770006 is designed and optimized for the highest performance to drive differential input ADCs.
Figure 35 shows a generic block diagram of the THS770006 driving an ADC. The primary interface circuit
between the amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means
to bias the signal to the input common-mode voltage required by the ADC. Filters range from single-order real
RC poles to higher-order LC filters, depending on the requirements of the application. Output resistors (R_O) are
shown on the amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
V_IN-
V_IN+
V_OCM
50W
50W
THS770006
100W
V_OCM
100W
V_OUT+
R_O
V_OUT-
R_O
Filter
and
Bias
A_IN+
ADC
A_{IN- CM}
Figure 35. Generic ADC Driver Block Diagram
The key points to consider for implementation are described in the following three subsections.
SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier + filter + ADC adds in RMS fashion. Noise from the amplifier is
bandwidth-limited by the filter. Depending on the amplitude of the signal and the bandwidth of the filter, the SNR
of the amplifier + filter can be calculated. To get the combined SNR, this value is then squared, added to the
square of the ADC SNR, and the square-root is taken. If the SNR of the amplifier + filter equals the SNR of the
ADC, the combined SNR is 3dB higher and for minimal inpact on the ADC's SNR the SNR of the amplifier + filter
should be 10dB or more lower. The combined SNR calculated in this manner is usually accurate to within ±1dB
of actual implementation.
SFDR Considerations
Theoretically, the spurious-free dynamic range (SFDR) of the amplifier + filter + ADC adds linearly on a
spur-by-spur basis. The amplifier output spurs are linearly related solely to the input signal and the SFDR is
usually set by second-order or third-order harmonic distortion for single-tone inputs, and by second-order or
third-order intermodulation distortion for two-tone inputs. Harmonic and second-order intermodulation distortion
can be filtered to some degree by the antialias filter, but not third-order intermodulation distortion. Generally, the
ADC also has the same distortion products, but as a result of the sampling nature and potential for clock
feedthrough, there may be spurs not linearly related solely to the input signal. When the spurs from the amplifier
+ filter are known, each can be directly added to the same spur from the ADC. This is a worst-case analysis
based on the assumption the spurs sources are in phase. If the spur of the amplifier + filter equals the spur of the
ADC, the combined spur is 6dB higher. The combined spur calculated in this manner is usually accurate to within
±6dB of actual implementation, but higher variations have been observed especially in second-order
performance as a result of phase shift in the filter.
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