TCA8418 Datasheet, PDF(20/37 Page) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

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TCA8418

SCPS215 â SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com

ROW

COL COL COL COL COL COL COL COL COL COL

X0 X0 X0 X0 X0 X0 X0 X0 X0 X0

X1 X1 X1 X1 X1 X1 X1 X1 X1 X1

X2 X2 X2 X2 X2 X2 X2 X2 X2 X2

X3 X3 X3 X3 X3 X3 X3 X3 X3 X3

X4 X4 X4 X4 X4 X4 X4 X4 X4 X4

X5 X5 X5 X5 X5 X5 X5 X5 X5 X5

X6 X6 X6 X6 X6 X6 X6 X6 X6 X6

X7 X7 X7 X7 X7 X7 X7 X7 X7 X7

The 18 GPIOs can be configured to support up to 80 keys. The GPIOs are programmed into rows (maximum of

8) and columns (maximum of 10) to support a keypad. This is done through writing to âKeypad or GPIO

Selectionâ registers (0x1D â 0x1F). The keypad in idle mode will be configured as Columns being driven low and

Rows as inputs with pull-ups.

When there is a key press or multiple key presses (Short between Column and Row), it will trigger an internal

state machine interrupt. The row that has a pressed key can be determined through reading the âGPIO Data

Statusâ registers (0x14-0x16).After that, the state machine starts a keyscan cycle to determine the column of the

key that was pressed. The state machine sets one column as an output low and all other columns as high. The

state machine will then walk a zero across the applicable row to determine what keys are being pressed.

Once a key has been pressed for 10ms, the state machine will set the appropriate key/s in the Key Event Status

the host processor. The state machine will continue to poll while there are keys pressed. If a key/s that was in

the key pressed register is released for 10ms or greater, the state machine will set the appropriate keys in the

Key Event Status register with the key pressed bit cleared. If K_IEN is set it will set the K_INT and generate an

interrupt to the host processor.

After receiving an interrupt, the host processor will first read the Interrupt Status register to determine what

interrupt caused the processor interrupt. It will then read the Key Event Register to see what keys where

pressed/released (Bits will then automatically clear on read in those registers). The processor will then write a 1

to the interrupt bit in the interrupt register to clear it and release the host interrupt to the processor. The

processor can see the status of what keys are pressed at any point by reading the KEY_EVENT_A register

(FIFO).

See Key Event Registers (FIFO) for more information.

When all Key_Event Registers are full, any additional events with set the OVR_FLOW_INT bit to 1. This will also

trigger an interrupt to the processor. When the FIFO is not full, new events are added to the next empty

Key_Event register in line. The OVR_FLOW_M bit sets the mode of operation during overflows. Clearing this bit

will cause new incoming events to be ignored and discarded. Setting this bit will overwrite old data with new data

starting with the first event.

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