TCA8418 Datasheet, PDF (10/37 Pages) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

TCA8418
SCPS215 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com
V_CC
V_POR
V_PORF
POR
Time
Time
Figure 4. V_POR
For proper operation of the power-on reset feature, use as directed in the figures and table above.
Interrupt Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the
ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the input port register.
The INT output has an open-drain structure and requires a pullup resistor to V_CC depending on the application. If
the INT signal is connected back to the processor that provides the SCL signal to the TCA64xxA, then the INT
pin has to be connected to V_CC. If not, the INT pin can be connected to V_CCP.
For more information on the interrupt output feature, see Control Register and Command Byte and Typical
Applications.
50 Micro-second Interrupt Configuration
The TCA8418 provides the capability of deasserting the interrupt for 50 µs while there is a pending event. When
the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already
asserted results in a 50 µs deassertion. When the INT_CFG bit is cleared, processor interrupt remains asserted
if the host tries to clear the interrupt. This feature is particularly useful for software development and edge
triggering applications.
I²C Interface
The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
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