MSP430C32X Datasheet, PDF (20/33 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430C32x, MSP430P325A
MIXED SIGNAL MICROCONTROLLER
SLAS219B – MARCH 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
current source (ADC)
PARAMETER
V(Rext) Voltage, (Rext)
R(ext) External resistor
∆IS
Load compliance
TEST CONDITIONS
V(Rext) = V(SVCC) – V(RI),
I(RI) = 6 mA,
VA0..A3 = 0 .. 0.4 × V(SVCC), IS =
V(Rext)/R(ext) = 1 mA
VA0..A3 = 0 .. 0.4 × V(SVCC),
IS = V(Rext)/R(ext) = 6 mA
VA0..A3 = 0 .. 0.5 × V(SVCC)
IS = V(Rext)/R(ext)= 1 mA
VA0..A3 = 0 .. 0.5 × V(SVCC)
IS = V(Rext)/R(ext)= 6 mA
VCC = 3 V/5 V,
VCC = 3 V/5 V
VCC = 3 V,
VCC = 3 V,
VCC = 5 V,
VCC = 5 V,
MIN
0.246 ×
V(SVCC)
95
TYP
0.249 ×
V(SVCC)
MAX
0.252 ×
V(SVCC)
1600
UNIT
V
Ω
–1
1 µA
–3.2
3.2 µA
–1.5
1.5 µA
–3.2
3.2 µA
A/D converter (f_(ADCLK) = 1 MHz)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Resolution
12 + 2
bits
f(con)
Conversion frequency
f(con) = f(ADCLK)
12-bit conversion
0.1
12+2-bit conversion ^{VCC = 3 V/5 V}
0.14
1.5
MHz
1.5
f(concyc)
Conversion cycles
12-bit conversion
f(ADCLK) = f(MCLK)/N _{12+2-bit conversion} VCC = 3 V/5 V
96
cycles of
132
ADCLK
LSB Voltage
INL1
INL2
INL3
INL4
DNL
Integral nonlinearity,
(see Note 18)
Differential nonlinearity,
(see Note 19)
0 ≤ DDV ≤ 127
128 ≤ DDV ≤ 255
256 ≤ DDV ≤ 2047
2048 ≤ DDV ≤ 4095
VCC = 3 V/5 V
0.000061×VSVCC
V
VCC = 3 V/5 V
–2
2
LSB
VCC = 3 V/5 V
–3
3
LSB
VCC = 3 V/5 V
–7
7
LSB
VCC = 3 V/5 V
–10
10
LSB
VCC = 3 V/5 V
–1
1
LSB
dN/dT
Temperature stability
V(Rext)/R(ext) = 6mA, Range A
Range B
VCC = 3 V/5 V
0.008
0.015
LSB/°C
dN/dV(SVCC) V(SVCC)rejection ratio
Range A, B, V(Rext)/R(ext) = 1 mA,
SVCC ±10%
Range A
VCC = 3 V/5 V
1.25
LSB/V
VCC = 3 V/5 V
–1.2
–0.49
0.24
% FSRA
(see Note 17)
Conversion offset 12 bit analog input to
digital value (see Note 16)
Range B
Range C
VCC = 3 V/5 V
–1.7
VCC = 3 V/5 V
–1.8
–0.6
0.49
% FSRB
(see Note 17)
–0.6
0.6
% FSRC
(see Note 17)
Range D
VCC = 3 V/5 V
–1.7
0.6
0.49
% FSRD
(see Note 17)
Conversion offset 14 bit analog input to
digital value (see Note 16)
Range ABCD
VCC = 3 V/5 V –0.27
–0.06
0.13
%FSRABCD
(see Note 17)
Slope 12 bit
Slope 14 bit
VCC = 3 V/5 V 0.9925
VCC = 3 V/5 V 0.9982
1 1.0075
1 1.0018
C(IN)
Input capacitance
VCC = 3 V/5 V
40
45
pF
R(SIN)
Serial input resistance
VCC = 3 V/5 V
2
kΩ
NOTES: 16. Offset referred to full scale 12/14 bit
17. FSRx: full scale range, separate for the four 12-bit ranges and the 14-bit (12+2) range.
18. DDV is short form of delta digital value. The DDV is a span of conversion results. It is assumed that the conversion is of 12 bit not
12+2 bit.
19. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.
20
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