DAC5573 Datasheet, PDF (20/30 Pages) Texas Instruments – QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER

DAC5573
SLAS401 – NOVEMBER 2003
www.ti.com
Master Transmitter Writing to a Slave Receiver (DAC5573) in HS Mode
When writing data to the DAC5573 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/W = 0) after which the DAC5573 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC5573. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5573 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I²C bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC5573 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC5573) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB 6
5
4
3
2
1
Master
Start
Master
0
0
0
0
1
X
X
NONE
Not acknowledge
Master
Repeated start
Master
1
0
0
1
1
A1
DAC5573
DAC5573 acknowledges
Master
0
0
Load 1 Load 0
0 Buff Sel 1
DAC5573
DAC5573 acknowledges
Master
D7 D6
D5
D4
D3
D2
DAC5573
DAC5573 acknowledges
Master
x
x
x
x
x
x
DAC5573
DAC5573 acknowledges
Master
Data or stop or repeated start⁽¹⁾
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB 6
5
4
3
2
Master
Start
Master
0
0
0
0
1
X
A0
Buff Sel 0
D1
x
1
X
NONE
Not acknowledge
Master
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
Repeated start
1
0
0
1
1
A1
A0
DAC5573 acknowledges
0
0
Load 1 Load 2
0 Buff Sel 1 Buff Sel 0
DAC5573 acknowledges
PD1 PD2
0
0
0
0
0
DAC5573 acknowledges
x
x
x
x
x
x
x
DAC5573 acknowledges
Stop or repeated start⁽¹⁾
LSB Comment
Begin sequence
X HS mode master code
No device may acknowledge HS mas-
ter code
R/W Write addressing (R/W=0)
PD0 Control byte (PD0=0)
D0 Writing data word, MSB
x Writing data word, LSB
Data or done ⁽²⁾
LSB Comment
Begin sequence
X HS mode master code
No device may acknowledge HS mas-
ter code
R/W Write addressing (R/W = 0)
PD0 Control byte (PD0=1)
0 Writing data word, high byte
x Writing data word, low byte
Done
(1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC5573 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
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