TMS45160 Datasheet, PDF (2/23 Pages) Texas Instruments – 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES

TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
operation
dual CAS
Two CAS pins ( LCAS– UCAS) are provided to give independent control of the 16 data I/O pins ( DQ0– DQ15)
with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. For read or write cycles, the
column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx
pins with data associated with the column address latched on the first falling xCAS edge. All address setup and
hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out
( see parameter t_CAC ) is measured from each individual xCAS to its corresponding DQx pins.
In order to latch in a new column address, both xCAS pins must be brought high. The column precharge time
( see parameter t_CP ) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, t_CLCH. During t_CLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet t_CAS minimum in order to ensure writing into
the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet t_CP .
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 512 columns specified by column
addresses A0 through A8 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The first falling edge
of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after t_RAH ( row-address hold time ) has been satisfied, usually
well in advance of the falling edge of xCAS. In this case, data is obtained after t_CAC max ( access time from xCAS
low) if t_AA max ( access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by t_CPA ( access time from rising edge of the last xCAS).
address ( A0– A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through
A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of
RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. W can be driven from the standard TTL circuits without a pullup resistor. The data input lines
are disabled when the read mode is selected. When W goes low prior to xCAS ( early write ) , data out remains
in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.
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