TMS416400 Datasheet, PDF (2/30 Pages) Texas Instruments – 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
description (continued)
The TMS4xx400 and TMS4xx400P are each offered in a 24 / 26-lead plastic surface-mount TSOP (DGA suffix)
package and a 24 / 26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized
for operation from 0°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by t_RASP, the maximum RAS low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column
address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after t_CAC max
(access time from CAS low) if t_AA max (access time from column address) and t_RAC have been satisfied. In the
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of t_CPA or t_CAC.
address: A0 – A11 ( TMS4x6400/ P) and A0 – A10 (TMS4x7400 / P)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. For the TMS4x6400 and
TMS4x6400P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11
row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address
bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS.
RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip select, activating the output buffers and latching the address bits into the column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ1 – DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t_CAC (which begins with
the negative transition of CAS) as long as t_RAC and t_AA are satisfied.
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