SN74AUP2G79 Datasheet, PDF (2/14 Pages) Texas Instruments – LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74AUP2G79
SCES755A – DECEMBER 2009 – REVISED DECEMBER 2009
www.ti.com
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting
the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽³⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000
SN74AUP2G79YFPR
__HW_
uQFN – DQE
Reel of 5000
SN74AUP2G79DQER
PT
QFN – RSE
Reel of 5000
SN74AUP2G79RSER
PREVIEW
SSOP – DCU
Reel of 3000
SN74AUP2G79DCUR
H79_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
CLK
D
OUTPUT
Q
↑
H
H
↑
L
L
L
X
Q₀
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
CLK
C
C
C
TG
Q
C
C
D
TG
TG
C
C
TG
C
C
C
Pin numbers shown are for the DCU and DQE packages.
2
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