SN74AUP2G79 Datasheet, PDF (1/14 Pages) Texas Instruments – LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74AUP2G79
www.ti.com
SCES755A – DECEMBER 2009 – REVISED DECEMBER 2009
LOW-POWER DUAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
Check for Samples: SN74AUP2G79
FEATURES
1
• Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption
(I_CC = 0.9 μA Maximum)
• Low Dynamic-Power Consumption
(C_pd = 3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• I_off Supports Partial-Power-Down Mode
Operation
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 4 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
1CLK
1D
2Q
GND
DCU PACKAGE
(TOP VIEW)
1
8
2
7
3
6
4
5
DQE PACKAGE
(TOP VIEW)
V
CC
1CLK ¹
1Q
1D ²
2Q ³
2D
GND ⁴
2CLK
V 8
CC
7 _1Q
6 _2D
5 _2CLK
RSE PACKAGE
YFP PACKAGE
(TOP VIEW)
(TOP VIEW)
1Q 1
V
CC
8
1CLK V A1 1 8 A2
CC
1D 1Q ^{B1 2 7 B2}
7 _{1CLK 2Q 2D C1 3 6 C2}
2D ²
6 _1D
GND ^{D1 4 5 D2} 2CLK
See mechanical drawings for dimensions.
2CLK ³ 4 ⁵ 2Q
GND
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
100%
100%
3.5
Switching Characteristics
at 25 MHz^(A)
80%
60%
40%
20%
3.3-V
Logic^(A)
80%
60%
40%
20%
3.3-V
Logic^(A)
3.0
2.5
2.0 ^Input
1.5
1.0
0.5
Output
0%
AAUUPP
0%
AUP
(A)
Single, dual, and triple gates
0.0
-0.5
0
5 10 15 20 25 30 35 40 45
Time (ns)
Figure 1. AUP – The Lowest-Power Family
(A) _{SN74AUP2Gxx data at CL = 15 pF.}
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated