SN74AUP1G80 Datasheet, PDF (2/14 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES593B – JULY 2004 – REVISED JULY 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP1G80YEPR
SN74AUP1G80YZPR
_ _ _HX_
SOT (SOT-23) – DBV
Reel of 3000
Reel of 250
SN74AUP1G80DBVR
SN74AUP1G80DBVT
H80_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G80DCKR
HX_
Reel of 250
SN74AUP1G80DCKT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
FUNCTION TABLE
INPUTS
CLK
D
↑
H
↑
L
L or H
X
OUTPUT
Q
L
H
Q₀
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
D
CLK
Q
Q
D
2