SN74AUP1G80 Datasheet, PDF (1/14 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74AUP1G80
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES593B – JULY 2004 – REVISED JULY 2005
FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Low Static-Power Consumption
(I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• I_off Supports Partial-Power-Down Mode
Operation
• Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 4.3 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• ESD Protection Exceeds ±5000 V With
Human-Body Model
D
CLK
DBV PACKAGE
(TOP VIEW)
1
5
2
V_CC
D
CLK
GND
DCK PACKAGE
(TOP VIEW)
1
5
V_CC
2
3
4Q
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND ^{3 4} Q
CLK ²
D ^{1 5} V_CC
GND
3
4
Q
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see Figure 2).
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
20%
20%
0%
AUP
0%
AUP
† _{Single, dual, and triple gates}
Figure 1. AUP – The Lowest-Power Family
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated