SLVA343A Datasheet, PDF (2/8 Pages) Texas Instruments – Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO

Introduction
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1 Introduction
In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential
problems and ensure reliable performance. Power supply designers must consider the timing and voltage
differences between core and input/output (I/O) voltage supplies during power-up and power-down
operations.
Sequencing refers to the order, timing, and differential in which the two voltage rails are powered up and
down. A system designed without proper sequencing may be at risk for two types of failures. The first of
these represents a threat to the long-term reliability of the dual voltage device, whereas the second is
more immediate, with the possibility of damaging interface circuits in the processor or system devices
such as memory, logic or data converter integrated circuits (IC).
Another potential problem with improper supply sequencing is bus contention. Bus contention is a
condition when the processor and another device both attempt to control a bidirectional bus during power
up. Bus contention may also affect I/O reliability. Power supply designers must check the requirements
regarding bus contention for individual devices.
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are
shown in Table 1. No specific voltage ramp rate is required for any of the supplies as long as the 3.3-V rail
never exceeds the 1.8-V rail by more than 2 V.
2 Power Requirements
The power requirements are as specified in Table 1.
Table 1. Power Requirements
PIN NAME
VOLTAGE ^{(1) (2)}
(V)
Imax
(mA)
TOLERANCE
SEQUENCING
ORDER
TIMING
DELAY
I/O
RTC_CVDD
1.2
1
–25%, +10%
1 ⁽³⁾
Core CVDD⁽⁴⁾
1 / 1.1 / 1.2
600
–9.75%, +10%
2
I/O
RVDD, PLL0_VDDA,
PLL1_VDDA, SATA_VDD,
USB_CVDD, USB0_VDDA12
1.2
200
–5%, +10%
3
I/O
USB0_VDDA18, USB1_VDDA18,
1.8
180
±5%
4
DDR_DVDD18, SATA_VDDR,
DVDD18
I/O
USB0_VDDA33, USB1_VDDA33
3.3
24
±5%
5
I/O
DVDD3318_A, DVDD3318_B,
DVDD3318_C
1.8 / 3.3
50 / 90⁽⁵⁾
±5%
4/5
(1) _{If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails}
(VDDA33_USB0/1).
(2) _{No specific voltage ramp rate is required for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) if STATIC18}
(USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) never exceeds more than 2 volts.
(3) _{If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.}
(4) _{If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.}
(5) _{If DVDD3318_A, B, and C are powered independently, maximum power for each rail is 1/3 the above maximum power.}
2
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
SLVA343A – June 2009 – Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated