LP38842-ADJ_15 Datasheet, PDF (2/15 Pages) Texas Instruments – 1.5A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors

LP38842-ADJ
SNVS304A – FEBRUARY 2005 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
ADJ 1
8 N/C
OUTPUT 2
7 INPUT
GND
BIAS 3
6 SHUTDOWN
GND 4
5 GND
SO PowerPAD-8, Top View
Pin Name
BIAS
OUTPUT
GND
INPUT
SHUTDOWN
ADJ
PIN DESCRIPTION
Description
The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and
provides drive voltage for the N-FET.
The regulated output voltage is connected to this pin.
This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-263
packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace
material and connected to circuit ground.
The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin.
Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred
millivolts above the output voltage.
This provides a low power shutdown function which turns the regulated output OFF. Tie to V_BIAS if this function is not
used.
The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 (see
TYPICAL APPLICATION CIRCUIT).
BLOCK DIAGRAM
Vbias
V_IN
UVLO
V_OUT
S/D
GND
-
++
V_REF
ADJ
2
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