CD54HC259_07 Datasheet, PDF (2/16 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Addressable Latch

Pinout
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
CD54HC259, CD54HCT259
(CERDIP)
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 V_CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9 Q4
Functional Diagram
1
A₀
A₁
2
1-OF-8
DECODER
3
A₂
14
LE
15
MR
13
D
8
LATCHES
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11
Q6
12
Q7
GND = 8
V_CC = 16
TRUTH TABLE
INPUTS
MR LE
OUTPUT OF
ADDRESS
LATCH
EACH OTHER
OUTPUT
FUNCTION
HL
D
Q_io
Addressable
Latch
HH
Q_io
LL
D
Q_io
Memory
L
8-Line
Demultiplexer
LH
L
L
Reset
H = High Voltage Level
L = Low Voltage Level
D = The level at the data input
Q_io = The level of Q_i (i = 0, 1...7, as appropriate) before the indicat-
ed steady-state input conditions were established.
LATCH SELECTION TABLE
SELECT INPUTS
A2
A1
A0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
LATCH
ADDRESSED
0
1
2
3
4
5
6
7
2