BQ3050 Datasheet, PDF (2/28 Pages) Texas Instruments – 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

bq3050
SLUSA92A – JANUARY 2011 – REVISED JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
T_A
–40°C to 85°C
PART
NUMBER
bq3050
ORDERING INFORMATION
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TSSOP-38
DBT
bq3050
ORDERING INFORMATION⁽¹⁾
TUBE ⁽²⁾
TAPE AND
REEL ⁽³⁾
bq3050DBT bq3050DBTR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
bq3050
TSSOP
UNITS
θ_{JA, High K}
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter
(6)
38 PINS
64.2
16.5
31.2
0.3
26.9
°C/W
θ_JC(bottom)
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Copyright © 2011, Texas Instruments Incorporated